From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933568AbcBYTIV (ORCPT ); Thu, 25 Feb 2016 14:08:21 -0500 Received: from down.free-electrons.com ([37.187.137.238]:53703 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933286AbcBYTIU (ORCPT ); Thu, 25 Feb 2016 14:08:20 -0500 Date: Thu, 25 Feb 2016 20:08:17 +0100 From: Alexandre Belloni To: Brian Norris Cc: Nicolas Ferre , Wenyou Yang , David Woodhouse , Josh Wu , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Boris Brezillon , devicetree@vger.kernel.org Subject: Re: [PATCH v3] mtd: atmel_nand: move the hsmc_clk from nfc node to nand node Message-ID: <20160225190817.GK12073@piout.net> References: <1456207220-7757-1-git-send-email-wenyou.yang@atmel.com> <56CC393B.6090801@atmel.com> <20160225183139.GL21465@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20160225183139.GL21465@google.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/02/2016 at 10:31:39 -0800, Brian Norris wrote : > + devicetree, Boris > > Convenient you left devicetree off, since I expect you'd get a hearty NAK > from them... > > On Tue, Feb 23, 2016 at 11:49:31AM +0100, Nicolas Ferre wrote: > > Le 23/02/2016 07:00, Wenyou Yang a écrit : > > > From: Josh Wu > > > > > > For SAMA5D3, SAMA5D4 SoC family, PMECC becomes a part of HSMC, they > > > need the HSMC clock enabled to work. > > > The NFC is a sub feature for current nand driver, it can be disabled. > > > But if HSMC clock is controlled by NFC, so disable NFC will also disable > > > the HSMC clock. then, it will make the PMECC fail to work. > > > > > > So the solution is move the HSMC clock out of NFC to nand node. When > > > nand driver probed, it will check whether the chip has HSMC, if yes then > > > it will require a HSMC clock. > > > > > > Add a new "atmel,sama5d3-nand" compatiable string for SAMA5D3's nand. > > > > > > Signed-off-by: Josh Wu > > > Signed-off-by: Wenyou Yang > > > --- > > > > > > Changes in v3: > > > - add "atmel,sama5d3-nand" compatiable string for SAMA5D3's nand. > > > - revert the mail address of Josh's Signed-off to the original. > > > > It seems okay now: > > Acked-by: Nicolas Ferre > > > > Brian, can we take this patch (if you acknowledged it) with us (through > > the arm-soc tree) to keep the synchronization with the DT part of this work? > > I will also consider squashing the DT part in this one as well as they > > cannot be separated. > > Doesn't that mean you have an illegal breakage of the device tree? > > Also, if you're going to refactor the binding (and possibly even break > it like this), why don't you address the comments Boris made back on the > first version about a year ago? > > http://patchwork.ozlabs.org/patch/438211/ > > Particularly, I agree that you seem to have the sub-node relationship > all backward. Why is the controller a sub-node of the flash node? And > you have no provision for multiple NAND chips? > Yes, we plan to break that binding even more, we don't have much choice. I would agree that it would be better to break it only once though. -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com