From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030296AbcBZRoM (ORCPT ); Fri, 26 Feb 2016 12:44:12 -0500 Received: from mail.skyhub.de ([78.46.96.112]:41584 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754324AbcBZRoK (ORCPT ); Fri, 26 Feb 2016 12:44:10 -0500 Date: Fri, 26 Feb 2016 18:44:02 +0100 From: Borislav Petkov To: Aravind Gopalakrishnan Cc: tony.luck@intel.com, hpa@zytor.com, mingo@redhat.com, tglx@linutronix.de, dougthompson@xmission.com, mchehab@osg.samsung.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, ashok.raj@intel.com, gong.chen@linux.intel.com, len.brown@intel.com, peterz@infradead.org, ak@linux.intel.com, alexander.shishkin@linux.intel.com Subject: Re: [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding Message-ID: <20160226174402.GF28911@pd.tnic> References: <1455659111-32074-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <1455659111-32074-5-git-send-email-Aravind.Gopalakrishnan@amd.com> <20160223123530.GB3673@pd.tnic> <56CDF5E4.4000206@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <56CDF5E4.4000206@amd.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 24, 2016 at 12:26:44PM -0600, Aravind Gopalakrishnan wrote: > Hmm, we call this from mce_threshold_block_init() with set_lvt_off = 1 to > write LVT offset value to MCi_MISC. > And we call this from store_interrupt_enable() to program APIC INT TYPE- > if (tr->b->interrupt_enable) > hi |= INT_TYPE_APIC; > > and from store_threshold_limit() to re-set the "error count"- > hi = (hi & ~MASK_ERR_COUNT_HI) | > (new_count & THRESHOLD_MAX); > > So I thought it fit the description as to "what" it does.. threshold_restart_bank() reprograms the MISC MSR after sanity-checking the fields supplied for that MSR. store_threshold_limit() sets the error count, store_interrupt_enable() enables/disables the interrupt and both call threshold_restart_bank() to do that. But this is basically spelling the code now - I don't think we need to comment in that detail. /* * Called via smp_call_function_single(), must be called with correct * cpu affinity. */ is also useless. > "This function provides user with capabilities to re-program the > 'thresold_limit' and 'interrupt_enable' sysfs attributes" No sorry, I don't want to be explaining every line. Just say: "Reprogram the MISC MSR behind this threshold bank." -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.