From: Vinod Koul <vinod.koul@intel.com>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Boris Brezillon" <boris.brezillon@free-electrons.com>,
"Dan Williams" <dan.j.williams@intel.com>,
dmaengine@vger.kernel.org, "Chen-Yu Tsai" <wens@csie.org>,
linux-sunxi@googlegroups.com,
"Emilio López" <emilio@elopez.com.ar>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users
Date: Tue, 8 Mar 2016 15:29:04 +0530 [thread overview]
Message-ID: <20160308095904.GM11154@localhost> (raw)
In-Reply-To: <20160308075131.GE8418@lukather>
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On Tue, Mar 08, 2016 at 08:51:31AM +0100, Maxime Ripard wrote:
> > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > + *
> > > > > > + * @para: contains information about block size and time before checking
> > > > > > + * DRQ line. This is device specific and only applicable to dedicated
> > > > > > + * DMA channels
> > > > >
> > > > > What information, can you elobrate.. And why can't you use existing
> > > > > dma_slave_config for this?
> > > >
> > > > Block size is related to the device FIFO size. I guess it allows the
> > > > DMA channel to launch a transfer of X bytes without having to check the
> > > > DRQ line (the line telling the DMA engine it can transfer more data
> > > > to/from the device). The wait cycles information is apparently related
> > > > to the number of clks the engine should wait before polling/checking
> > > > the DRQ line status between each block transfer. I'm not sure what it
> > > > saves to put WAIT_CYCLES() to something != 1, but in their BSP,
> > > > Allwinner tweak that depending on the device.
> >
> > we already have block size aka src/dst_maxburst, why not use that one.
>
> I'm not sure it's really the same thing. The DMA controller also has a
> burst parameter, that is either 1 byte or 8 bytes, and ends up being
> different from this one.
Nope that is buswidth. maxburst is words which cna be sent to device FIFO.
>
> > Why does dmaengine need to wait? Can you explain that
>
> We have no idea, we thought you might have one :)
Well that is hardware dependent. From DMAengine API usage we dont ahve to
wait at all. We should submit next descriptor as soon as possible.
> It doesn't really makes sense to us, but it does have a significant
> impact on the throughput.
--
~Vinod
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next prev parent reply other threads:[~2016-03-08 9:55 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 9:59 [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users Boris Brezillon
2016-03-07 14:54 ` Vinod Koul
2016-03-07 15:08 ` Boris Brezillon
2016-03-07 20:30 ` Maxime Ripard
2016-03-08 2:55 ` Vinod Koul
2016-03-08 2:59 ` Vinod Koul
2016-03-08 7:51 ` Maxime Ripard
2016-03-08 8:42 ` [linux-sunxi] " Hans de Goede
2016-03-08 10:05 ` Vinod Koul
2016-03-09 10:58 ` Maxime Ripard
2016-03-08 8:46 ` Boris Brezillon
2016-03-08 9:10 ` [linux-sunxi] " Priit Laes
2016-03-08 10:04 ` Vinod Koul
2016-03-09 10:08 ` [linux-sunxi] " LABBE Corentin
2016-03-08 9:59 ` Vinod Koul [this message]
2016-03-09 10:14 ` Boris Brezillon
2016-03-11 6:24 ` Vinod Koul
2016-03-11 9:40 ` Boris Brezillon
2016-03-11 10:06 ` Vinod Koul
2016-03-11 10:26 ` Boris Brezillon
2016-03-11 11:21 ` Vinod Koul
2016-03-09 11:06 ` Boris Brezillon
2016-03-11 6:26 ` Vinod Koul
2016-03-11 9:45 ` Boris Brezillon
2016-03-11 10:09 ` Vinod Koul
2016-03-11 10:55 ` Maxime Ripard
2016-03-11 11:18 ` Vinod Koul
2016-03-14 11:46 ` Maxime Ripard
2016-03-16 3:22 ` Vinod Koul
2016-03-07 15:30 ` [linux-sunxi] " Priit Laes
2016-03-07 15:47 ` Boris Brezillon
2016-03-07 17:15 ` Emilio López
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