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From: Borislav Petkov <>
To: Andy Lutomirski <>
Cc: Huang Rui <>,
	Peter Zijlstra <>,, X86 ML <>,
	LKML <>
Subject: [PATCH] x86/delay: Avoid preemptible context checks in delay_mwaitx()
Date: Wed, 9 Mar 2016 21:56:22 +0100
Message-ID: <20160309205622.GG6564@pd.tnic> (raw)
In-Reply-To: <20160309181003.GF6564@pd.tnic>

We do use this_cpu_ptr(&cpu_tss) as a cacheline-aligned, seldomly
accessed per-cpu var as the MONITORX target in delay_mwaitx(). However,
when called in preemptible context, this_cpu_ptr -> smp_processor_id() ->
debug_smp_processor_id() fires:

  BUG: using smp_processor_id() in preemptible [00000000] code: udevd/312
  caller is delay_mwaitx+0x40/0xa0

But we don't care about that check - we only need cpu_tss as a MONITORX
target and it doesn't really matter which CPU's var we're touching as
we're going idle anyway. Fix that.

Suggested-by: Andy Lutomirski <>
Signed-off-by: Borislav Petkov <>
Cc: Huang Rui <>
 arch/x86/lib/delay.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c
index e912b2f6d36e..2f07c291dcc8 100644
--- a/arch/x86/lib/delay.c
+++ b/arch/x86/lib/delay.c
@@ -102,7 +102,7 @@ static void delay_mwaitx(unsigned long __loops)
 		 * Use cpu_tss as a cacheline-aligned, seldomly
 		 * accessed per-cpu variable as the monitor target.
-		__monitorx(this_cpu_ptr(&cpu_tss), 0, 0);
+		__monitorx(raw_cpu_ptr(&cpu_tss), 0, 0);
 		 * AMD, like Intel, supports the EAX hint and EAX=0xf


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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-09 11:37 [RFC PATCH] x86/delay: Do not use cpu_tss in preemptible ctxt " Borislav Petkov
2016-03-09 17:56 ` Andy Lutomirski
2016-03-09 18:10   ` Borislav Petkov
2016-03-09 20:56     ` Borislav Petkov [this message]
2016-03-10 11:07       ` [tip:x86/urgent] x86/delay: Avoid preemptible context checks " tip-bot for Borislav Petkov

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