From: Ingo Molnar <mingo@kernel.org>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: "H. Peter Anvin" <hpa@linux.intel.com>,
Ingo Molnar <mingo@elte.hu>, Thomas Gleixner <tglx@linutronix.de>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH]x86/cpufeatures.h: Enumerate A Few New AVX-512 Features
Date: Thu, 10 Mar 2016 11:28:11 +0100 [thread overview]
Message-ID: <20160310102811.GC21593@gmail.com> (raw)
In-Reply-To: <1457558030-50118-1-git-send-email-fenghua.yu@intel.com>
* Fenghua Yu <fenghua.yu@intel.com> wrote:
> From: Fenghua Yu <fenghua.yu@intel.com>
>
> A few new AVX-512 instruction groups/features are added in cpufeatures.h
> for enuermation: AVX512DQ, AVX512BW, and AVX512VL.
>
> The specification for latest AVX-512 including the features can be found at
> https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> ---
> arch/x86/include/asm/cpufeature.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 7ad8c94..71a5cc4 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -219,6 +219,7 @@
> #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
> #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
> #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
> +#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ Instructions */
> #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
> #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
> #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
> @@ -229,6 +230,8 @@
> #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
> #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
> #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
> +#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW Instructions */
> +#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 Vector Lengths */
>
> /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
> #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
In the latest x86 tree these defines are in cpufeatures.h, not cpufeature.h.
Thanks,
Ingo
prev parent reply other threads:[~2016-03-10 10:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-09 21:13 [PATCH]x86/cpufeatures.h: Enumerate A Few New AVX-512 Features Fenghua Yu
2016-03-10 10:28 ` Ingo Molnar [this message]
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