From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933471AbcCaUkE (ORCPT ); Thu, 31 Mar 2016 16:40:04 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:33332 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932647AbcCaUj6 (ORCPT ); Thu, 31 Mar 2016 16:39:58 -0400 Date: Thu, 31 Mar 2016 13:39:42 -0700 From: Mark Brown To: Laxman Dewangan Cc: Bjorn Andersson , Bjorn Andersson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Liam Girdwood , Stephen Warren , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gandhar Dighe , Stuart Yates Message-ID: <20160331203942.GV2350@sirena.org.uk> References: <20160331174741.GO2350@sirena.org.uk> <56FD62BA.3040406@nvidia.com> <20160331183130.GR2350@sirena.org.uk> <56FD6CF7.5080909@nvidia.com> <20160331184553.GS2350@sirena.org.uk> <56FD6ED6.3020507@nvidia.com> <20160331185945.GT2350@sirena.org.uk> <56FD7379.2000307@nvidia.com> <20160331192227.GU2350@sirena.org.uk> <56FD7F07.7010404@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="qCb2VTfFGdRLn6RH" Content-Disposition: inline In-Reply-To: <56FD7F07.7010404@nvidia.com> X-Cookie: If anything can go wrong, it will. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 64.55.107.4 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --qCb2VTfFGdRLn6RH Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Apr 01, 2016 at 01:18:23AM +0530, Laxman Dewangan wrote: > On Friday 01 April 2016 12:52 AM, Mark Brown wrote: > >So why doesn't the device end up configuring 100mV/us when asked for > >50mv/us? That's reasonably expected - the configured ramp rate is a > >maximum rate given that this is used to limit inrush current. > We did this to adjust device configuration to nearest higher side but this > is not working well on some of cases. > On same device, DCDC (SD) rails support 4 ramp configurations, 13.75mV/us, > 27.5mV/us, 55mV/us and 100mV/us. > HW team measured the ramp time at 7.5mV/us when device configured at > 27.5mV/uS. > So as per above, it will be adjusted to 13.75mV/us (nearest higher side) for > device configuration but this device need to configure for 27.5mV/us. You're saying that the device is so bad at regulating the ramp rate that it's not only failing to keep up with the desired ramp rate and capping at whatever rate but it's also doing even worse if configured for a slower rate? That's not great, it sounds like it's doing the ramp control via some sort of dead reckoning thing rather than by actually ramping the voltage it's trying to regulate like it was asked to. Is the error in the observed values a function of the capacitance that we can calcuate here? --qCb2VTfFGdRLn6RH Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJW/YsJAAoJECTWi3JdVIfQb2kH/2Tc7Lhv8rnj7OiEUuvO6Lys vn3A2MwOFl3H6MJmp1kMwzO6KR67kF/pFSohVKG85vNKBoqVJQg74NqvtoP52Cie FLbf1YBWs+r5NXegK/dx4RXJdLL6ZEU7PxddnOKY/Od3AsQPDPgpVYbh2o9uDpdf inCyRboZCt1bVFfPBi/gWUsLqo/3sPhYp0552++HRotz1lSt00VI6tBgngiJmNEH GfFJcNzoS3NoYi8iHTz1cdyZmAedWK2GL0rhb9D0uQSDscrlerijlYa1V3WePx1J 2z+p/gCaaiWn6vwvEceZ+ecYfr2MNBhUoTLPKfwqw0C4MGiPdrl0pbZaU2w5veY= =v42+ -----END PGP SIGNATURE----- --qCb2VTfFGdRLn6RH--