From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752653AbcEYXIo (ORCPT ); Wed, 25 May 2016 19:08:44 -0400 Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:58399 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751931AbcEYXIm (ORCPT ); Wed, 25 May 2016 19:08:42 -0400 Date: Wed, 25 May 2016 19:08:31 -0400 From: Rich Felker To: Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, Ian Campbell , Jason Cooper , Kumar Gala , Marc Zyngier , Pawel Moll , Rob Herring , Thomas Gleixner Subject: Re: [PATCH v3 03/12] of: add J-Core interrupt controller bindings Message-ID: <20160525230831.GU21636@brightrain.aerifal.cx> References: <03e22cb9679aa7d45f07dba0bf6610ec824cae11.1464148904.git.dalias@libc.org> <20160525102503.GG1337@leverpostej> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160525102503.GG1337@leverpostej> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 25, 2016 at 11:25:04AM +0100, Mark Rutland wrote: > On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote: > > Signed-off-by: Rich Felker > > --- > > .../bindings/interrupt-controller/jcore,aic.txt | 29 ++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > > new file mode 100644 > > index 0000000..5dc99b9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > > @@ -0,0 +1,29 @@ > > +J-Core Advanced Interrupt Controller > > + > > +Required properties: > > + > > +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic > > + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for > > + the "aic2" core with 64 interrupts. > > + > > +- reg : Memory region for configuration. > > + > > +- interrupt-controller : Identifies the node as an interrupt controller > > + > > +- #interrupt-cells : Specifies the number of cells needed to encode an > > + interrupt source. The value shall be 1. > > + > > +Optional properties: > > + > > +- cpu-offset : For SMP, the offset to the per-cpu memory region for > > + configuration, to be scaled by the cpu number. > > I take is that "cpu number" means the "sequential, zero-based hardware > cpu id" defined in patch 2. I would recommend that you explicitly > mention that (e.g. here say "hardware cpu id" rather than "cpu number"), > so as to not have this confused with Linux logical IDs. OK. The current arch/sh SMP framework only has nominal support for hw cpuid != logical cpuid; it's not actually used/usable right now. But the DT binding spec should be clear on this anyway. Rich