From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932638AbcFARfL (ORCPT ); Wed, 1 Jun 2016 13:35:11 -0400 Received: from mga09.intel.com ([134.134.136.24]:22126 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756057AbcFARez (ORCPT ); Wed, 1 Jun 2016 13:34:55 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,402,1459839600"; d="scan'208";a="993185687" Subject: [PATCH 3/5] x86, rapl: use Intel family macros for rapl To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, Dave Hansen , dave.hansen@linux.intel.com, srinivas.pandruvada@linux.intel.com, peterz@infradead.org From: Dave Hansen Date: Wed, 01 Jun 2016 10:34:43 -0700 References: <20160601173440.4BF4BE10@viggo.jf.intel.com> In-Reply-To: <20160601173440.4BF4BE10@viggo.jf.intel.com> Message-Id: <20160601173443.269E7110@viggo.jf.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dave Hansen Use the new INTEL_FAM6_MODEL_* macros for rapl.c. Note that this is missing at least one Westmere model and Skylake Server. The resulting binary structure 'rapl_cpu_match' is the same before and after this patch. Signed-off-by: Dave Hansen Cc: Srinivas Pandruvada Cc: Peter Zijlstra --- b/arch/x86/events/intel/rapl.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff -puN arch/x86/events/intel/rapl.c~x86-intel-familites-rapl arch/x86/events/intel/rapl.c --- a/arch/x86/events/intel/rapl.c~x86-intel-familites-rapl 2016-06-01 10:20:11.655351115 -0700 +++ b/arch/x86/events/intel/rapl.c 2016-06-01 10:20:11.660351341 -0700 @@ -55,6 +55,7 @@ #include #include #include +#include #include "../perf_event.h" MODULE_LICENSE("GPL"); @@ -786,26 +787,26 @@ static const struct intel_rapl_init_fun }; static const struct x86_cpu_id rapl_cpu_match[] __initconst = { - X86_RAPL_MODEL_MATCH(42, snb_rapl_init), /* Sandy Bridge */ - X86_RAPL_MODEL_MATCH(45, snbep_rapl_init), /* Sandy Bridge-EP */ + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SANDYBRIDGE, snb_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SANDYBRIDGE_X, snbep_rapl_init), - X86_RAPL_MODEL_MATCH(58, snb_rapl_init), /* Ivy Bridge */ - X86_RAPL_MODEL_MATCH(62, snbep_rapl_init), /* IvyTown */ + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_IVYBRIDGE, snb_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_IVYBRIDGE_X, snbep_rapl_init), - X86_RAPL_MODEL_MATCH(60, hsw_rapl_init), /* Haswell */ - X86_RAPL_MODEL_MATCH(63, hsx_rapl_init), /* Haswell-Server */ - X86_RAPL_MODEL_MATCH(69, hsw_rapl_init), /* Haswell-Celeron */ - X86_RAPL_MODEL_MATCH(70, hsw_rapl_init), /* Haswell GT3e */ - - X86_RAPL_MODEL_MATCH(61, hsw_rapl_init), /* Broadwell */ - X86_RAPL_MODEL_MATCH(71, hsw_rapl_init), /* Broadwell-H */ - X86_RAPL_MODEL_MATCH(79, hsx_rapl_init), /* Broadwell-Server */ - X86_RAPL_MODEL_MATCH(86, hsx_rapl_init), /* Broadwell Xeon D */ + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_CORE, hsw_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_X, hsw_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_ULT, hsw_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_GT3E, hsw_rapl_init), + + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_CORE_M, hsw_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_GT3E, hsw_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_X, hsw_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_XEON_D, hsw_rapl_init), - X86_RAPL_MODEL_MATCH(87, knl_rapl_init), /* Knights Landing */ + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_XEON_PHI_KNL, knl_rapl_init), - X86_RAPL_MODEL_MATCH(78, skl_rapl_init), /* Skylake */ - X86_RAPL_MODEL_MATCH(94, skl_rapl_init), /* Skylake H/S */ + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_MOBILE, skl_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, skl_rapl_init), {}, }; _