[PATCH 01/20] x86, intel: Introduce macros for Intel family numbers

[PATCH 01/20] x86, intel: Introduce macros for Intel family numbers

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

If you are cc'd on this code, please check _your_ code vs. the
model list in "intel-family.h".  Please make sure you have all
the models listed that you intend to.

Problem:

We have a boatload of open-coded family-6 model numbers.  Half of
them have these model numbers in hex and the other half in
decimal.  This makes grepping for them tons of fun, if you were
to try.

Solution:

Consolidate all the magic numbers.  Put all the definitions in
one header.

The names here are closely derived from the comments describing
the models from arch/x86/events/intel/core.c.  We could easily
make them shorter by doing things like s/SANDYBRIDGE/SNB/, but
they seemed fine even with the longer versions to me.

Do not take any of these names too literally, like "DESKTOP"
or "MOBILE".  These are all colloquial names and not precise
descriptions of everywhere a given model will show up.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Doug Thompson <dougthompson@xmission.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Len Brown <lenb@kernel.org>
Cc: linux-acpi@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Cc: linux-mmc@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: platform-driver-x86@vger.kernel.org
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Souvik Kumar Chakravarty <souvik.k.chakravarty@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vishwanath Somayaji <vishwanath.somayaji@intel.com>
Cc: Yan, Zheng <zheng.z.yan@intel.com>
Cc: Zhang Rui <rui.zhang@intel.com>

---

 b/arch/x86/include/asm/intel-family.h |   57 ++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff -puN /dev/null arch/x86/include/asm/intel-family.h
--- /dev/null	2016-04-04 09:40:43.435149254 -0700
+++ b/arch/x86/include/asm/intel-family.h	2016-06-01 15:45:02.877884645 -0700
@@ -0,0 +1,57 @@
+#ifndef _ASM_X86_INTEL_FAMILY_H
+#define _ASM_X86_INTEL_FAMILY_H
+
+/*
+ * "Big Core" Processors (Branded as Core, Xeon, etc...)
+ *
+ * The "_X" parts are generally the EP and EX Xeons, or the
+ * "Extreme" ones, like Broadwell-E.
+ */
+
+#define INTEL_FAM6_MODEL_CORE_YONAH		0x0E
+#define INTEL_FAM6_MODEL_CORE2_MEROM		0x0F
+#define INTEL_FAM6_MODEL_CORE2_MEROM_L		0x16
+#define INTEL_FAM6_MODEL_CORE2_PENRYN		0x17
+#define INTEL_FAM6_MODEL_CORE2_DUNNINGTON	0x1D
+#define INTEL_FAM6_MODEL_NEHALEM		0x1E
+#define INTEL_FAM6_MODEL_NEHALEM_EP		0x1A
+#define INTEL_FAM6_MODEL_NEHALEM_EX		0x2E
+#define INTEL_FAM6_MODEL_WESTMERE		0x25
+#define INTEL_FAM6_MODEL_WESTMERE_EP		0x2C
+#define INTEL_FAM6_MODEL_WESTMERE_EX		0x2F
+#define INTEL_FAM6_MODEL_SANDYBRIDGE		0x2A
+#define INTEL_FAM6_MODEL_SANDYBRIDGE_X		0x2D
+#define INTEL_FAM6_MODEL_IVYBRIDGE		0x3A
+#define INTEL_FAM6_MODEL_IVYBRIDGE_X		0x3E
+#define INTEL_FAM6_MODEL_HASWELL_CORE		0x3C
+#define INTEL_FAM6_MODEL_HASWELL_X		0x3F
+#define INTEL_FAM6_MODEL_HASWELL_ULT		0x45
+#define INTEL_FAM6_MODEL_HASWELL_GT3E		0x46
+#define INTEL_FAM6_MODEL_BROADWELL_CORE_M	0x3D
+#define INTEL_FAM6_MODEL_BROADWELL_XEON_D	0x56
+#define INTEL_FAM6_MODEL_BROADWELL_GT3E		0x47
+#define INTEL_FAM6_MODEL_BROADWELL_X		0x4F
+#define INTEL_FAM6_MODEL_SKYLAKE_MOBILE		0x4E
+#define INTEL_FAM6_MODEL_SKYLAKE_DESKTOP	0x5E
+#define INTEL_FAM6_MODEL_SKYLAKE_X		0x55
+#define INTEL_FAM6_MODEL_KABYLAKE_MOBILE	0x8E
+#define INTEL_FAM6_MODEL_KABYLAKE_DESKTOP	0x9E
+
+/* "Small Core" Processors (Atom) */
+
+#define INTEL_FAM6_MODEL_ATOM_PINEVIEW		0x1C
+#define INTEL_FAM6_MODEL_ATOM_LINCROFT		0x26
+#define INTEL_FAM6_MODEL_ATOM_PENWELL		0x27
+#define INTEL_FAM6_MODEL_ATOM_CLOVERVIEW	0x35
+#define INTEL_FAM6_MODEL_ATOM_CEDARVIEW		0x36
+#define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37
+#define INTEL_FAM6_MODEL_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
+#define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C
+#define INTEL_FAM6_MODEL_ATOM_GOLDMONT		0x5C
+#define INTEL_FAM6_MODEL_ATOM_DENVERTON		0x5F /* Goldmont Microserver */
+
+/* Xeon Phi */
+
+#define INTEL_FAM6_MODEL_XEON_PHI_KNL		0x57 /* Knights Landing */
+
+#endif /* _ASM_X86_INTEL_FAMILY_H */
_

[PATCH 02/20] x86, perf: use Intel family macros for core perf events

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Use the new model number macros instead of spelling things out
in the comments.

Note that this is missing a Nehalem model that is mentioned in
intel_idle which is fixed up in a later patch.

The resulting binary (arch/x86/events/intel/core.o) is exactly
the same with and without this patch modulo some harmless changes
to restoring %esi in the return path of functions, even those
untouched by this patch.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: "Yan, Zheng" <zheng.z.yan@intel.com>
---

 b/arch/x86/events/intel/core.c |   87 ++++++++++++++++++++---------------------
 1 file changed, 44 insertions(+), 43 deletions(-)

diff -puN arch/x86/events/intel/core.c~x86-intel-families-core-events arch/x86/events/intel/core.c
--- a/arch/x86/events/intel/core.c~x86-intel-families-core-events	2016-06-01 15:45:03.301903980 -0700
+++ b/arch/x86/events/intel/core.c	2016-06-01 15:45:03.310904391 -0700
@@ -16,6 +16,7 @@
 
 #include <asm/cpufeature.h>
 #include <asm/hardirq.h>
+#include <asm/intel-family.h>
 #include <asm/apic.h>
 
 #include "../perf_event.h"
@@ -3261,11 +3262,11 @@ static int intel_snb_pebs_broken(int cpu
 	u32 rev = UINT_MAX; /* default to broken for unknown models */
 
 	switch (cpu_data(cpu).x86_model) {
-	case 42: /* SNB */
+	case INTEL_FAM6_MODEL_SANDYBRIDGE:
 		rev = 0x28;
 		break;
 
-	case 45: /* SNB-EP */
+	case INTEL_FAM6_MODEL_SANDYBRIDGE_X:
 		switch (cpu_data(cpu).x86_mask) {
 		case 6: rev = 0x618; break;
 		case 7: rev = 0x70c; break;
@@ -3508,15 +3509,15 @@ __init int intel_pmu_init(void)
 	 * Install the hw-cache-events table:
 	 */
 	switch (boot_cpu_data.x86_model) {
-	case 14: /* 65nm Core "Yonah" */
+	case INTEL_FAM6_MODEL_CORE_YONAH:
 		pr_cont("Core events, ");
 		break;
 
-	case 15: /* 65nm Core2 "Merom"          */
+	case INTEL_FAM6_MODEL_CORE2_MEROM:
 		x86_add_quirk(intel_clovertown_quirk);
-	case 22: /* 65nm Core2 "Merom-L"        */
-	case 23: /* 45nm Core2 "Penryn"         */
-	case 29: /* 45nm Core2 "Dunnington (MP) */
+	case INTEL_FAM6_MODEL_CORE2_MEROM_L:
+	case INTEL_FAM6_MODEL_CORE2_PENRYN:
+	case INTEL_FAM6_MODEL_CORE2_DUNNINGTON:
 		memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 
@@ -3527,9 +3528,9 @@ __init int intel_pmu_init(void)
 		pr_cont("Core2 events, ");
 		break;
 
-	case 30: /* 45nm Nehalem    */
-	case 26: /* 45nm Nehalem-EP */
-	case 46: /* 45nm Nehalem-EX */
+	case INTEL_FAM6_MODEL_NEHALEM:
+	case INTEL_FAM6_MODEL_NEHALEM_EP:
+	case INTEL_FAM6_MODEL_NEHALEM_EX:
 		memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
@@ -3557,11 +3558,11 @@ __init int intel_pmu_init(void)
 		pr_cont("Nehalem events, ");
 		break;
 
-	case 28: /* 45nm Atom "Pineview"   */
-	case 38: /* 45nm Atom "Lincroft"   */
-	case 39: /* 32nm Atom "Penwell"    */
-	case 53: /* 32nm Atom "Cloverview" */
-	case 54: /* 32nm Atom "Cedarview"  */
+	case INTEL_FAM6_MODEL_ATOM_PINEVIEW:
+	case INTEL_FAM6_MODEL_ATOM_LINCROFT:
+	case INTEL_FAM6_MODEL_ATOM_PENWELL:
+	case INTEL_FAM6_MODEL_ATOM_CLOVERVIEW:
+	case INTEL_FAM6_MODEL_ATOM_CEDARVIEW:
 		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 
@@ -3573,9 +3574,9 @@ __init int intel_pmu_init(void)
 		pr_cont("Atom events, ");
 		break;
 
-	case 55: /* 22nm Atom "Silvermont"                */
-	case 76: /* 14nm Atom "Airmont"                   */
-	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
+	case INTEL_FAM6_MODEL_ATOM_SILVERMONT1:
+	case INTEL_FAM6_MODEL_ATOM_SILVERMONT2:
+	case INTEL_FAM6_MODEL_ATOM_AIRMONT:
 		memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
 			sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
@@ -3590,8 +3591,8 @@ __init int intel_pmu_init(void)
 		pr_cont("Silvermont events, ");
 		break;
 
-	case 92: /* 14nm Atom "Goldmont" */
-	case 95: /* 14nm Atom "Goldmont Denverton" */
+	case INTEL_FAM6_MODEL_ATOM_GOLDMONT:
+	case INTEL_FAM6_MODEL_ATOM_DENVERTON:
 		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
@@ -3614,9 +3615,9 @@ __init int intel_pmu_init(void)
 		pr_cont("Goldmont events, ");
 		break;
 
-	case 37: /* 32nm Westmere    */
-	case 44: /* 32nm Westmere-EP */
-	case 47: /* 32nm Westmere-EX */
+	case INTEL_FAM6_MODEL_WESTMERE:
+	case INTEL_FAM6_MODEL_WESTMERE_EP:
+	case INTEL_FAM6_MODEL_WESTMERE_EX:
 		memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
@@ -3643,8 +3644,8 @@ __init int intel_pmu_init(void)
 		pr_cont("Westmere events, ");
 		break;
 
-	case 42: /* 32nm SandyBridge         */
-	case 45: /* 32nm SandyBridge-E/EN/EP */
+	case INTEL_FAM6_MODEL_SANDYBRIDGE:
+	case INTEL_FAM6_MODEL_SANDYBRIDGE_X:
 		x86_add_quirk(intel_sandybridge_quirk);
 		x86_add_quirk(intel_ht_bug);
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
@@ -3657,7 +3658,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.event_constraints = intel_snb_event_constraints;
 		x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
 		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
-		if (boot_cpu_data.x86_model == 45)
+		if (boot_cpu_data.x86_model == INTEL_FAM6_MODEL_SANDYBRIDGE_X)
 			x86_pmu.extra_regs = intel_snbep_extra_regs;
 		else
 			x86_pmu.extra_regs = intel_snb_extra_regs;
@@ -3679,8 +3680,8 @@ __init int intel_pmu_init(void)
 		pr_cont("SandyBridge events, ");
 		break;
 
-	case 58: /* 22nm IvyBridge       */
-	case 62: /* 22nm IvyBridge-EP/EX */
+	case INTEL_FAM6_MODEL_IVYBRIDGE:
+	case INTEL_FAM6_MODEL_IVYBRIDGE_X:
 		x86_add_quirk(intel_ht_bug);
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
@@ -3696,7 +3697,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
 		x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
 		x86_pmu.pebs_prec_dist = true;
-		if (boot_cpu_data.x86_model == 62)
+		if (boot_cpu_data.x86_model == INTEL_FAM6_MODEL_IVYBRIDGE_X)
 			x86_pmu.extra_regs = intel_snbep_extra_regs;
 		else
 			x86_pmu.extra_regs = intel_snb_extra_regs;
@@ -3714,10 +3715,10 @@ __init int intel_pmu_init(void)
 		break;
 
 
-	case 60: /* 22nm Haswell Core */
-	case 63: /* 22nm Haswell Server */
-	case 69: /* 22nm Haswell ULT */
-	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
+	case INTEL_FAM6_MODEL_HASWELL_CORE:
+	case INTEL_FAM6_MODEL_HASWELL_X:
+	case INTEL_FAM6_MODEL_HASWELL_ULT:
+	case INTEL_FAM6_MODEL_HASWELL_GT3E:
 		x86_add_quirk(intel_ht_bug);
 		x86_pmu.late_ack = true;
 		memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -3741,10 +3742,10 @@ __init int intel_pmu_init(void)
 		pr_cont("Haswell events, ");
 		break;
 
-	case 61: /* 14nm Broadwell Core-M */
-	case 86: /* 14nm Broadwell Xeon D */
-	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
-	case 79: /* 14nm Broadwell Server */
+	case INTEL_FAM6_MODEL_BROADWELL_CORE_M:
+	case INTEL_FAM6_MODEL_BROADWELL_XEON_D:
+	case INTEL_FAM6_MODEL_BROADWELL_GT3E:
+	case INTEL_FAM6_MODEL_BROADWELL_X:
 		x86_pmu.late_ack = true;
 		memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
@@ -3777,7 +3778,7 @@ __init int intel_pmu_init(void)
 		pr_cont("Broadwell events, ");
 		break;
 
-	case 87: /* Knights Landing Xeon Phi */
+	case INTEL_FAM6_MODEL_XEON_PHI_KNL:
 		memcpy(hw_cache_event_ids,
 		       slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs,
@@ -3795,11 +3796,11 @@ __init int intel_pmu_init(void)
 		pr_cont("Knights Landing events, ");
 		break;
 
-	case 142: /* 14nm Kabylake Mobile */
-	case 158: /* 14nm Kabylake Desktop */
-	case 78: /* 14nm Skylake Mobile */
-	case 94: /* 14nm Skylake Desktop */
-	case 85: /* 14nm Skylake Server */
+	case INTEL_FAM6_MODEL_SKYLAKE_MOBILE:
+	case INTEL_FAM6_MODEL_SKYLAKE_DESKTOP:
+	case INTEL_FAM6_MODEL_SKYLAKE_X:
+	case INTEL_FAM6_MODEL_KABYLAKE_MOBILE:
+	case INTEL_FAM6_MODEL_KABYLAKE_DESKTOP:
 		x86_pmu.late_ack = true;
 		memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
_

[PATCH 03/20] x86, rapl: use Intel family macros for rapl

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Use the new INTEL_FAM6_MODEL_* macros for rapl.c.

Note that this is missing at least one Westmere model and Skylake
Server which will we fixed later in this series.

The resulting binary structure 'rapl_cpu_match' is the same
before and after this patch.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
---

 b/arch/x86/events/intel/rapl.c |   33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff -puN arch/x86/events/intel/rapl.c~x86-intel-familites-rapl arch/x86/events/intel/rapl.c
--- a/arch/x86/events/intel/rapl.c~x86-intel-familites-rapl	2016-06-01 15:45:03.751924503 -0700
+++ b/arch/x86/events/intel/rapl.c	2016-06-01 15:45:03.756924730 -0700
@@ -55,6 +55,7 @@
 #include <linux/slab.h>
 #include <linux/perf_event.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include "../perf_event.h"
 
 MODULE_LICENSE("GPL");
@@ -786,26 +787,26 @@ static const struct intel_rapl_init_fun
 };
 
 static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
-	X86_RAPL_MODEL_MATCH(42, snb_rapl_init),	/* Sandy Bridge */
-	X86_RAPL_MODEL_MATCH(45, snbep_rapl_init),	/* Sandy Bridge-EP */
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SANDYBRIDGE, snb_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SANDYBRIDGE_X, snbep_rapl_init),
 
-	X86_RAPL_MODEL_MATCH(58, snb_rapl_init),	/* Ivy Bridge */
-	X86_RAPL_MODEL_MATCH(62, snbep_rapl_init),	/* IvyTown */
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_IVYBRIDGE, snb_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_IVYBRIDGE_X, snbep_rapl_init),
 
-	X86_RAPL_MODEL_MATCH(60, hsw_rapl_init),	/* Haswell */
-	X86_RAPL_MODEL_MATCH(63, hsx_rapl_init),	/* Haswell-Server */
-	X86_RAPL_MODEL_MATCH(69, hsw_rapl_init),	/* Haswell-Celeron */
-	X86_RAPL_MODEL_MATCH(70, hsw_rapl_init),	/* Haswell GT3e */
-
-	X86_RAPL_MODEL_MATCH(61, hsw_rapl_init),	/* Broadwell */
-	X86_RAPL_MODEL_MATCH(71, hsw_rapl_init),	/* Broadwell-H */
-	X86_RAPL_MODEL_MATCH(79, hsx_rapl_init),	/* Broadwell-Server */
-	X86_RAPL_MODEL_MATCH(86, hsx_rapl_init),	/* Broadwell Xeon D */
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_CORE, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_X, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_ULT, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_GT3E, hsw_rapl_init),
+
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_CORE_M, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_GT3E, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_X, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_XEON_D, hsw_rapl_init),
 
-	X86_RAPL_MODEL_MATCH(87, knl_rapl_init),	/* Knights Landing */
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_XEON_PHI_KNL, knl_rapl_init),
 
-	X86_RAPL_MODEL_MATCH(78, skl_rapl_init),	/* Skylake */
-	X86_RAPL_MODEL_MATCH(94, skl_rapl_init),	/* Skylake H/S */
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_MOBILE, skl_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, skl_rapl_init),
 	{},
 };
 
_

[PATCH 04/20] x86, intel_idle: use Intel family macros for intel_idle

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Use the new INTEL_FAM6_MODEL_* macros for intel_idle.c.  Also fix
up some of the macros to be consistent with how some of the
intel_idle code refers to the model.

There's on oddity here: model 0x1F is uniquely referred to here
and nowhere else that I could find.  0x1E/0x1F are just spelled
out as "Intel Core i7 and i5 Processors" in the SDM or as "Intel
processors based on the Nehalem, Westmere microarchitectures" in
the RDPMC section.  Comments between tables 19-19 and 19-20 in
the SDM seem to point to 0x1F being some kind of Westmere, so
let's call it "WESTMERE2".

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Len Brown <lenb@kernel.org>
Cc: linux-pm@vger.kernel.org
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---

 b/arch/x86/include/asm/intel-family.h |   10 +++-
 b/drivers/idle/intel_idle.c           |   71 +++++++++++++++++-----------------
 2 files changed, 43 insertions(+), 38 deletions(-)

diff -puN arch/x86/include/asm/intel-family.h~x86-intel-familites-intelidle arch/x86/include/asm/intel-family.h
--- a/arch/x86/include/asm/intel-family.h~x86-intel-familites-intelidle	2016-06-01 15:45:04.180944067 -0700
+++ b/arch/x86/include/asm/intel-family.h	2016-06-01 15:45:04.187944386 -0700
@@ -6,6 +6,9 @@
  *
  * The "_X" parts are generally the EP and EX Xeons, or the
  * "Extreme" ones, like Broadwell-E.
+ *
+ * Things ending in "2" are usually because we have no better
+ * name for them.  There's no processor called "WESTMERE2".
  */
 
 #define INTEL_FAM6_MODEL_CORE_YONAH		0x0E
@@ -17,12 +20,13 @@
 #define INTEL_FAM6_MODEL_NEHALEM_EP		0x1A
 #define INTEL_FAM6_MODEL_NEHALEM_EX		0x2E
 #define INTEL_FAM6_MODEL_WESTMERE		0x25
+#define INTEL_FAM6_MODEL_WESTMERE2		0x1F
 #define INTEL_FAM6_MODEL_WESTMERE_EP		0x2C
 #define INTEL_FAM6_MODEL_WESTMERE_EX		0x2F
 #define INTEL_FAM6_MODEL_SANDYBRIDGE		0x2A
 #define INTEL_FAM6_MODEL_SANDYBRIDGE_X		0x2D
 #define INTEL_FAM6_MODEL_IVYBRIDGE		0x3A
-#define INTEL_FAM6_MODEL_IVYBRIDGE_X		0x3E
+#define INTEL_FAM6_MODEL_IVYBRIDGE_X		0x3E /* aka. Ivy Town / IVT */
 #define INTEL_FAM6_MODEL_HASWELL_CORE		0x3C
 #define INTEL_FAM6_MODEL_HASWELL_X		0x3F
 #define INTEL_FAM6_MODEL_HASWELL_ULT		0x45
@@ -44,9 +48,9 @@
 #define INTEL_FAM6_MODEL_ATOM_PENWELL		0x27
 #define INTEL_FAM6_MODEL_ATOM_CLOVERVIEW	0x35
 #define INTEL_FAM6_MODEL_ATOM_CEDARVIEW		0x36
-#define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37
+#define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT */
 #define INTEL_FAM6_MODEL_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
-#define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C
+#define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C /* CherryTrail */
 #define INTEL_FAM6_MODEL_ATOM_GOLDMONT		0x5C
 #define INTEL_FAM6_MODEL_ATOM_DENVERTON		0x5F /* Goldmont Microserver */
 
diff -puN drivers/idle/intel_idle.c~x86-intel-familites-intelidle drivers/idle/intel_idle.c
--- a/drivers/idle/intel_idle.c~x86-intel-familites-intelidle	2016-06-01 15:45:04.182944158 -0700
+++ b/drivers/idle/intel_idle.c	2016-06-01 15:45:04.189944477 -0700
@@ -62,6 +62,7 @@
 #include <linux/cpu.h>
 #include <linux/module.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/mwait.h>
 #include <asm/msr.h>
 
@@ -1020,38 +1021,38 @@ static const struct idle_cpu idle_cpu_bx
 	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 
 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
-	ICPU(0x1a, idle_cpu_nehalem),
-	ICPU(0x1e, idle_cpu_nehalem),
-	ICPU(0x1f, idle_cpu_nehalem),
-	ICPU(0x25, idle_cpu_nehalem),
-	ICPU(0x2c, idle_cpu_nehalem),
-	ICPU(0x2e, idle_cpu_nehalem),
-	ICPU(0x1c, idle_cpu_atom),
-	ICPU(0x26, idle_cpu_lincroft),
-	ICPU(0x2f, idle_cpu_nehalem),
-	ICPU(0x2a, idle_cpu_snb),
-	ICPU(0x2d, idle_cpu_snb),
-	ICPU(0x36, idle_cpu_atom),
-	ICPU(0x37, idle_cpu_byt),
-	ICPU(0x4c, idle_cpu_cht),
-	ICPU(0x3a, idle_cpu_ivb),
-	ICPU(0x3e, idle_cpu_ivt),
-	ICPU(0x3c, idle_cpu_hsw),
-	ICPU(0x3f, idle_cpu_hsw),
-	ICPU(0x45, idle_cpu_hsw),
-	ICPU(0x46, idle_cpu_hsw),
-	ICPU(0x4d, idle_cpu_avn),
-	ICPU(0x3d, idle_cpu_bdw),
-	ICPU(0x47, idle_cpu_bdw),
-	ICPU(0x4f, idle_cpu_bdw),
-	ICPU(0x56, idle_cpu_bdw),
-	ICPU(0x4e, idle_cpu_skl),
-	ICPU(0x5e, idle_cpu_skl),
-	ICPU(0x8e, idle_cpu_skl),
-	ICPU(0x9e, idle_cpu_skl),
-	ICPU(0x55, idle_cpu_skx),
-	ICPU(0x57, idle_cpu_knl),
-	ICPU(0x5c, idle_cpu_bxt),
+	ICPU(INTEL_FAM6_MODEL_NEHALEM_EP,	idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_NEHALEM,		idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_WESTMERE2,	idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_WESTMERE,		idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_WESTMERE_EP,	idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_NEHALEM_EX,	idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_ATOM_PINEVIEW,	idle_cpu_atom),
+	ICPU(INTEL_FAM6_MODEL_ATOM_LINCROFT,	idle_cpu_lincroft),
+	ICPU(INTEL_FAM6_MODEL_WESTMERE_EX,	idle_cpu_nehalem),
+	ICPU(INTEL_FAM6_MODEL_SANDYBRIDGE,	idle_cpu_snb),
+	ICPU(INTEL_FAM6_MODEL_SANDYBRIDGE_X,	idle_cpu_snb),
+	ICPU(INTEL_FAM6_MODEL_ATOM_CEDARVIEW,	idle_cpu_atom),
+	ICPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1,	idle_cpu_byt),
+	ICPU(INTEL_FAM6_MODEL_ATOM_AIRMONT,	idle_cpu_cht),
+	ICPU(INTEL_FAM6_MODEL_IVYBRIDGE,	idle_cpu_ivb),
+	ICPU(INTEL_FAM6_MODEL_IVYBRIDGE_X,	idle_cpu_ivt),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_CORE,	idle_cpu_hsw),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_X,	idle_cpu_hsw),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_ULT,	idle_cpu_hsw),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_GT3E,	idle_cpu_hsw),
+	ICPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT2,	idle_cpu_avn),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_CORE_M,	idle_cpu_bdw),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_GT3E,	idle_cpu_bdw),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_X,	idle_cpu_bdw),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_XEON_D,	idle_cpu_bdw),
+	ICPU(INTEL_FAM6_MODEL_SKYLAKE_MOBILE,	idle_cpu_skl),
+	ICPU(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP,	idle_cpu_skl),
+	ICPU(INTEL_FAM6_MODEL_KABYLAKE_MOBILE,	idle_cpu_skl),
+	ICPU(INTEL_FAM6_MODEL_KABYLAKE_DESKTOP,	idle_cpu_skl),
+	ICPU(INTEL_FAM6_MODEL_SKYLAKE_X,	idle_cpu_skx),
+	ICPU(INTEL_FAM6_MODEL_XEON_PHI_KNL,	idle_cpu_knl),
+	ICPU(INTEL_FAM6_MODEL_ATOM_GOLDMONT,	idle_cpu_bxt),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
@@ -1261,13 +1262,13 @@ static void intel_idle_state_table_updat
 {
 	switch (boot_cpu_data.x86_model) {
 
-	case 0x3e: /* IVT */
+	case INTEL_FAM6_MODEL_IVYBRIDGE_X:
 		ivt_idle_state_table_update();
 		break;
-	case 0x5c: /* BXT */
+	case INTEL_FAM6_MODEL_ATOM_GOLDMONT:
 		bxt_idle_state_table_update();
 		break;
-	case 0x5e: /* SKL-H */
+	case INTEL_FAM6_MODEL_SKYLAKE_DESKTOP:
 		sklh_idle_state_table_update();
 		break;
 	}
_

[PATCH 05/20] x86, msr: use Intel family macros for msr events code

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Use the new INTEL_FAM6_MODEL_* macros for arch/x86/events/msr.c.

This code appears to be missing handling for "WESTMERE2" and
"SKYLAKE_X".

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
---

 b/arch/x86/events/msr.c |   59 ++++++++++++++++++++++++------------------------
 1 file changed, 30 insertions(+), 29 deletions(-)

diff -puN arch/x86/events/msr.c~x86-intel-familites-msr arch/x86/events/msr.c
--- a/arch/x86/events/msr.c~x86-intel-familites-msr	2016-06-01 15:45:04.638964953 -0700
+++ b/arch/x86/events/msr.c	2016-06-01 15:45:04.643965181 -0700
@@ -1,4 +1,5 @@
 #include <linux/perf_event.h>
+#include <asm/intel-family.h>
 
 enum perf_msr_id {
 	PERF_MSR_TSC			= 0,
@@ -34,39 +35,39 @@ static bool test_intel(int idx)
 		return false;
 
 	switch (boot_cpu_data.x86_model) {
-	case 30: /* 45nm Nehalem    */
-	case 26: /* 45nm Nehalem-EP */
-	case 46: /* 45nm Nehalem-EX */
-
-	case 37: /* 32nm Westmere    */
-	case 44: /* 32nm Westmere-EP */
-	case 47: /* 32nm Westmere-EX */
-
-	case 42: /* 32nm SandyBridge         */
-	case 45: /* 32nm SandyBridge-E/EN/EP */
-
-	case 58: /* 22nm IvyBridge       */
-	case 62: /* 22nm IvyBridge-EP/EX */
-
-	case 60: /* 22nm Haswell Core */
-	case 63: /* 22nm Haswell Server */
-	case 69: /* 22nm Haswell ULT */
-	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
-
-	case 61: /* 14nm Broadwell Core-M */
-	case 86: /* 14nm Broadwell Xeon D */
-	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
-	case 79: /* 14nm Broadwell Server */
-
-	case 55: /* 22nm Atom "Silvermont"                */
-	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
-	case 76: /* 14nm Atom "Airmont"                   */
+	case INTEL_FAM6_MODEL_NEHALEM:
+	case INTEL_FAM6_MODEL_NEHALEM_EP:
+	case INTEL_FAM6_MODEL_NEHALEM_EX:
+
+	case INTEL_FAM6_MODEL_WESTMERE:
+	case INTEL_FAM6_MODEL_WESTMERE_EP:
+	case INTEL_FAM6_MODEL_WESTMERE_EX:
+
+	case INTEL_FAM6_MODEL_SANDYBRIDGE:
+	case INTEL_FAM6_MODEL_SANDYBRIDGE_X:
+
+	case INTEL_FAM6_MODEL_IVYBRIDGE:
+	case INTEL_FAM6_MODEL_IVYBRIDGE_X:
+
+	case INTEL_FAM6_MODEL_HASWELL_CORE:
+	case INTEL_FAM6_MODEL_HASWELL_X:
+	case INTEL_FAM6_MODEL_HASWELL_ULT:
+	case INTEL_FAM6_MODEL_HASWELL_GT3E:
+
+	case INTEL_FAM6_MODEL_BROADWELL_CORE_M:
+	case INTEL_FAM6_MODEL_BROADWELL_XEON_D:
+	case INTEL_FAM6_MODEL_BROADWELL_GT3E:
+	case INTEL_FAM6_MODEL_BROADWELL_X:
+
+	case INTEL_FAM6_MODEL_ATOM_SILVERMONT1:
+	case INTEL_FAM6_MODEL_ATOM_SILVERMONT2:
+	case INTEL_FAM6_MODEL_ATOM_AIRMONT:
 		if (idx == PERF_MSR_SMI)
 			return true;
 		break;
 
-	case 78: /* 14nm Skylake Mobile */
-	case 94: /* 14nm Skylake Desktop */
+	case INTEL_FAM6_MODEL_SKYLAKE_MOBILE:
+	case INTEL_FAM6_MODEL_SKYLAKE_DESKTOP:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;
_

[PATCH 06/20] x86, msr: add missing Intel models

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

This patch presumes that Kabylake and Skylake Server will be the
same as the existing Skylake parts and adds them to the MSR
events code.

Also add handling for "WESTMERE2".

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
---

 b/arch/x86/events/msr.c |    4 ++++
 1 file changed, 4 insertions(+)

diff -puN arch/x86/events/msr.c~x86-intel-familites-msr-fix arch/x86/events/msr.c
--- a/arch/x86/events/msr.c~x86-intel-familites-msr-fix	2016-06-01 15:45:05.061984244 -0700
+++ b/arch/x86/events/msr.c	2016-06-01 15:45:05.064984381 -0700
@@ -40,6 +40,7 @@ static bool test_intel(int idx)
 	case INTEL_FAM6_MODEL_NEHALEM_EX:
 
 	case INTEL_FAM6_MODEL_WESTMERE:
+	case INTEL_FAM6_MODEL_WESTMERE2:
 	case INTEL_FAM6_MODEL_WESTMERE_EP:
 	case INTEL_FAM6_MODEL_WESTMERE_EX:
 
@@ -68,6 +69,9 @@ static bool test_intel(int idx)
 
 	case INTEL_FAM6_MODEL_SKYLAKE_MOBILE:
 	case INTEL_FAM6_MODEL_SKYLAKE_DESKTOP:
+	case INTEL_FAM6_MODEL_SKYLAKE_X:
+	case INTEL_FAM6_MODEL_KABYLAKE_MOBILE:
+	case INTEL_FAM6_MODEL_KABYLAKE_DESKTOP:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;
_

[PATCH 07/20] x86, intel: use Intel model macros intead of open-coding

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Use the new macros to remove another large set of open-coded values.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: linux-pm@vger.kernel.org
---

 b/arch/x86/include/asm/intel-family.h |    4 ++-
 b/drivers/powercap/intel_rapl.c       |   43 +++++++++++++++++-----------------
 2 files changed, 25 insertions(+), 22 deletions(-)

diff -puN arch/x86/include/asm/intel-family.h~x86-intel-familites-powercap-rapl arch/x86/include/asm/intel-family.h
--- a/arch/x86/include/asm/intel-family.h~x86-intel-familites-powercap-rapl	2016-06-01 15:45:05.485003534 -0700
+++ b/arch/x86/include/asm/intel-family.h	2016-06-01 15:45:05.490003762 -0700
@@ -48,10 +48,12 @@
 #define INTEL_FAM6_MODEL_ATOM_PENWELL		0x27
 #define INTEL_FAM6_MODEL_ATOM_CLOVERVIEW	0x35
 #define INTEL_FAM6_MODEL_ATOM_CEDARVIEW		0x36
+#define INTEL_FAM6_MODEL_ATOM_MERRIFIELD1	0x4A /* Tangier */
+#define INTEL_FAM6_MODEL_ATOM_MERRIFIELD2	0x5A /* Annidale */
 #define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT */
 #define INTEL_FAM6_MODEL_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
 #define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C /* CherryTrail */
-#define INTEL_FAM6_MODEL_ATOM_GOLDMONT		0x5C
+#define INTEL_FAM6_MODEL_ATOM_GOLDMONT		0x5C /* Broxton */
 #define INTEL_FAM6_MODEL_ATOM_DENVERTON		0x5F /* Goldmont Microserver */
 
 /* Xeon Phi */
diff -puN drivers/powercap/intel_rapl.c~x86-intel-familites-powercap-rapl drivers/powercap/intel_rapl.c
--- a/drivers/powercap/intel_rapl.c~x86-intel-familites-powercap-rapl	2016-06-01 15:45:05.486003580 -0700
+++ b/drivers/powercap/intel_rapl.c	2016-06-01 15:45:05.490003762 -0700
@@ -33,6 +33,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 
 /* Local defines */
 #define MSR_PLATFORM_POWER_LIMIT	0x0000065C
@@ -1096,27 +1097,27 @@ static const struct rapl_defaults rapl_d
 		}
 
 static const struct x86_cpu_id rapl_ids[] __initconst = {
-	RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
-	RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
-	RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */
-	RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
-	RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
-	RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
-	RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
-	RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
-	RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
-	RAPL_CPU(0x46, rapl_defaults_core),/* Haswell */
-	RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
-	RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
-	RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
-	RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
-	RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
-	RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
-	RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
-	RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
-	RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
-	RAPL_CPU(0x8E, rapl_defaults_core),/* Kabylake */
-	RAPL_CPU(0x9E, rapl_defaults_core),/* Kabylake */
+	RAPL_CPU(INTEL_FAM6_MODEL_SANDYBRIDGE,		rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_SANDYBRIDGE_X,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1,	rapl_defaults_byt),
+	RAPL_CPU(INTEL_FAM6_MODEL_IVYBRIDGE,		rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_CORE,		rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_CORE_M,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_X,		rapl_defaults_hsw_server),
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_X,		rapl_defaults_hsw_server),
+	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_ULT,		rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_GT3E,		rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_GT3E,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_MOBILE,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_AIRMONT,		rapl_defaults_cht),
+	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_MERRIFIELD1,	rapl_defaults_tng),
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_XEON_D,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_MERRIFIELD2,	rapl_defaults_ann),
+	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_GOLDMONT,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_XEON_PHI_KNL,		rapl_defaults_hsw_server),
+	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_MOBILE,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_DESKTOP,	rapl_defaults_core),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
_

[PATCH 08/20] x86, rapl: reorder cpu detection table

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Let's make an effort to group these things by microarchitecture
name.  It makes it easier to see if something got missed.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: linux-pm@vger.kernel.org
---

 b/drivers/powercap/intel_rapl.c |   22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff -puN drivers/powercap/intel_rapl.c~x86-intel-familites-powercap-rapl-reorder drivers/powercap/intel_rapl.c
--- a/drivers/powercap/intel_rapl.c~x86-intel-familites-powercap-rapl-reorder	2016-06-01 15:45:05.931023874 -0700
+++ b/drivers/powercap/intel_rapl.c	2016-06-01 15:45:05.936024102 -0700
@@ -1099,25 +1099,31 @@ static const struct rapl_defaults rapl_d
 static const struct x86_cpu_id rapl_ids[] __initconst = {
 	RAPL_CPU(INTEL_FAM6_MODEL_SANDYBRIDGE,		rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_SANDYBRIDGE_X,	rapl_defaults_core),
-	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1,	rapl_defaults_byt),
+
 	RAPL_CPU(INTEL_FAM6_MODEL_IVYBRIDGE,		rapl_defaults_core),
+
 	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_CORE,		rapl_defaults_core),
-	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_CORE_M,	rapl_defaults_core),
-	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_X,		rapl_defaults_hsw_server),
-	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_X,		rapl_defaults_hsw_server),
 	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_ULT,		rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_GT3E,		rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_HASWELL_X,		rapl_defaults_hsw_server),
+
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_CORE_M,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_GT3E,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_XEON_D,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_X,		rapl_defaults_hsw_server),
+
+	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_MOBILE,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_MOBILE,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_DESKTOP,	rapl_defaults_core),
+
+	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1,	rapl_defaults_byt),
 	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_AIRMONT,		rapl_defaults_cht),
 	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_MERRIFIELD1,	rapl_defaults_tng),
-	RAPL_CPU(INTEL_FAM6_MODEL_BROADWELL_XEON_D,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_MERRIFIELD2,	rapl_defaults_ann),
 	RAPL_CPU(INTEL_FAM6_MODEL_ATOM_GOLDMONT,	rapl_defaults_core),
-	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP,	rapl_defaults_core),
+
 	RAPL_CPU(INTEL_FAM6_MODEL_XEON_PHI_KNL,		rapl_defaults_hsw_server),
-	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_MOBILE,	rapl_defaults_core),
-	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_DESKTOP,	rapl_defaults_core),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
_

[PATCH 09/20] x86, platform: use new Intel model number macros

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Remove the open-coded model numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---

 b/arch/x86/include/asm/intel-family.h       |    4 ++--
 b/arch/x86/platform/atom/punit_atom_debug.c |    5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff -puN arch/x86/include/asm/intel-family.h~x86-intel-familites-punit arch/x86/include/asm/intel-family.h
--- a/arch/x86/include/asm/intel-family.h~x86-intel-familites-punit	2016-06-01 15:45:06.354043164 -0700
+++ b/arch/x86/include/asm/intel-family.h	2016-06-01 15:45:06.359043392 -0700
@@ -50,9 +50,9 @@
 #define INTEL_FAM6_MODEL_ATOM_CEDARVIEW		0x36
 #define INTEL_FAM6_MODEL_ATOM_MERRIFIELD1	0x4A /* Tangier */
 #define INTEL_FAM6_MODEL_ATOM_MERRIFIELD2	0x5A /* Annidale */
-#define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT */
+#define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT / Valleyview */
 #define INTEL_FAM6_MODEL_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
-#define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C /* CherryTrail */
+#define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C /* CherryTrail / Braswell */
 #define INTEL_FAM6_MODEL_ATOM_GOLDMONT		0x5C /* Broxton */
 #define INTEL_FAM6_MODEL_ATOM_DENVERTON		0x5F /* Goldmont Microserver */
 
diff -puN arch/x86/platform/atom/punit_atom_debug.c~x86-intel-familites-punit arch/x86/platform/atom/punit_atom_debug.c
--- a/arch/x86/platform/atom/punit_atom_debug.c~x86-intel-familites-punit	2016-06-01 15:45:06.356043255 -0700
+++ b/arch/x86/platform/atom/punit_atom_debug.c	2016-06-01 15:45:06.359043392 -0700
@@ -23,6 +23,7 @@
 #include <linux/seq_file.h>
 #include <linux/io.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/iosf_mbi.h>
 
 /* Power gate status reg */
@@ -143,8 +144,8 @@ static void punit_dbgfs_unregister(void)
 	  (kernel_ulong_t)&drv_data }
 
 static const struct x86_cpu_id intel_punit_cpu_ids[] = {
-	ICPU(55, punit_device_byt), /* Valleyview, Bay Trail */
-	ICPU(76, punit_device_cht), /* Braswell, Cherry Trail */
+	ICPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1, punit_device_byt),
+	ICPU(INTEL_FAM6_MODEL_ATOM_AIRMONT, punit_device_cht),
 	{}
 };
 
_

[PATCH 10/20] x86, cstate: use Intel Model name macros

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

This should be getting old by now.  Use the new macros intead of
open-coded magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kan Liang <kan.liang@intel.com>
---

 b/arch/x86/events/intel/cstate.c |   47 +++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 23 deletions(-)

diff -puN arch/x86/events/intel/cstate.c~x86-intel-familites-cstate arch/x86/events/intel/cstate.c
--- a/arch/x86/events/intel/cstate.c~x86-intel-familites-cstate	2016-06-01 15:45:06.804063686 -0700
+++ b/arch/x86/events/intel/cstate.c	2016-06-01 15:45:06.807063823 -0700
@@ -89,6 +89,7 @@
 #include <linux/slab.h>
 #include <linux/perf_event.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include "../perf_event.h"
 
 MODULE_LICENSE("GPL");
@@ -511,37 +512,37 @@ static const struct cstate_model slm_cst
 	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
 
 static const struct x86_cpu_id intel_cstates_match[] __initconst = {
-	X86_CSTATES_MODEL(30, nhm_cstates),    /* 45nm Nehalem              */
-	X86_CSTATES_MODEL(26, nhm_cstates),    /* 45nm Nehalem-EP           */
-	X86_CSTATES_MODEL(46, nhm_cstates),    /* 45nm Nehalem-EX           */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_NEHALEM,    nhm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_NEHALEM_EP, nhm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_NEHALEM_EX, nhm_cstates),
 
-	X86_CSTATES_MODEL(37, nhm_cstates),    /* 32nm Westmere             */
-	X86_CSTATES_MODEL(44, nhm_cstates),    /* 32nm Westmere-EP          */
-	X86_CSTATES_MODEL(47, nhm_cstates),    /* 32nm Westmere-EX          */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_WESTMERE,    nhm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_WESTMERE_EP, nhm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_WESTMERE_EX, nhm_cstates),
 
-	X86_CSTATES_MODEL(42, snb_cstates),    /* 32nm SandyBridge          */
-	X86_CSTATES_MODEL(45, snb_cstates),    /* 32nm SandyBridge-E/EN/EP  */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SANDYBRIDGE,   snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SANDYBRIDGE_X, snb_cstates),
 
-	X86_CSTATES_MODEL(58, snb_cstates),    /* 22nm IvyBridge            */
-	X86_CSTATES_MODEL(62, snb_cstates),    /* 22nm IvyBridge-EP/EX      */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_IVYBRIDGE,   snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_IVYBRIDGE_X, snb_cstates),
 
-	X86_CSTATES_MODEL(60, snb_cstates),    /* 22nm Haswell Core         */
-	X86_CSTATES_MODEL(63, snb_cstates),    /* 22nm Haswell Server       */
-	X86_CSTATES_MODEL(70, snb_cstates),    /* 22nm Haswell + GT3e       */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_CORE, snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_X,	 snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_GT3E, snb_cstates),
 
-	X86_CSTATES_MODEL(69, hswult_cstates), /* 22nm Haswell ULT          */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_ULT, hswult_cstates),
 
-	X86_CSTATES_MODEL(55, slm_cstates),    /* 22nm Atom Silvermont      */
-	X86_CSTATES_MODEL(77, slm_cstates),    /* 22nm Atom Avoton/Rangely  */
-	X86_CSTATES_MODEL(76, slm_cstates),    /* 22nm Atom Airmont         */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_ATOM_SILVERMONT1, slm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_ATOM_SILVERMONT2, slm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_ATOM_AIRMONT,     slm_cstates),
 
-	X86_CSTATES_MODEL(61, snb_cstates),    /* 14nm Broadwell Core-M     */
-	X86_CSTATES_MODEL(86, snb_cstates),    /* 14nm Broadwell Xeon D     */
-	X86_CSTATES_MODEL(71, snb_cstates),    /* 14nm Broadwell + GT3e     */
-	X86_CSTATES_MODEL(79, snb_cstates),    /* 14nm Broadwell Server     */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_CORE_M, snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_XEON_D, snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_GT3E,   snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_X,      snb_cstates),
 
-	X86_CSTATES_MODEL(78, snb_cstates),    /* 14nm Skylake Mobile       */
-	X86_CSTATES_MODEL(94, snb_cstates),    /* 14nm Skylake Desktop      */
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SKYLAKE_MOBILE,  snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, snb_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
_

[PATCH 11/20] x86, uncore: use Intel family name macros for uncore

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
---

 b/arch/x86/events/intel/uncore.c |   41 +++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff -puN arch/x86/events/intel/uncore.c~x86-intel-familites-uncore arch/x86/events/intel/uncore.c
--- a/arch/x86/events/intel/uncore.c~x86-intel-familites-uncore	2016-06-01 15:45:07.229083068 -0700
+++ b/arch/x86/events/intel/uncore.c	2016-06-01 15:45:07.238083478 -0700
@@ -1,4 +1,5 @@
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include "uncore.h"
 
 static struct intel_uncore_type *empty_uncore[] = { NULL, };
@@ -1365,26 +1366,26 @@ static const struct intel_uncore_init_fu
 };
 
 static const struct x86_cpu_id intel_uncore_match[] __initconst = {
-	X86_UNCORE_MODEL_MATCH(26, nhm_uncore_init),	/* Nehalem */
-	X86_UNCORE_MODEL_MATCH(30, nhm_uncore_init),
-	X86_UNCORE_MODEL_MATCH(37, nhm_uncore_init),	/* Westmere */
-	X86_UNCORE_MODEL_MATCH(44, nhm_uncore_init),
-	X86_UNCORE_MODEL_MATCH(42, snb_uncore_init),	/* Sandy Bridge */
-	X86_UNCORE_MODEL_MATCH(58, ivb_uncore_init),	/* Ivy Bridge */
-	X86_UNCORE_MODEL_MATCH(60, hsw_uncore_init),	/* Haswell */
-	X86_UNCORE_MODEL_MATCH(69, hsw_uncore_init),	/* Haswell Celeron */
-	X86_UNCORE_MODEL_MATCH(70, hsw_uncore_init),	/* Haswell */
-	X86_UNCORE_MODEL_MATCH(61, bdw_uncore_init),	/* Broadwell */
-	X86_UNCORE_MODEL_MATCH(71, bdw_uncore_init),	/* Broadwell */
-	X86_UNCORE_MODEL_MATCH(45, snbep_uncore_init),	/* Sandy Bridge-EP */
-	X86_UNCORE_MODEL_MATCH(46, nhmex_uncore_init),	/* Nehalem-EX */
-	X86_UNCORE_MODEL_MATCH(47, nhmex_uncore_init),	/* Westmere-EX aka. Xeon E7 */
-	X86_UNCORE_MODEL_MATCH(62, ivbep_uncore_init),	/* Ivy Bridge-EP */
-	X86_UNCORE_MODEL_MATCH(63, hswep_uncore_init),	/* Haswell-EP */
-	X86_UNCORE_MODEL_MATCH(79, bdx_uncore_init),	/* BDX-EP */
-	X86_UNCORE_MODEL_MATCH(86, bdx_uncore_init),	/* BDX-DE */
-	X86_UNCORE_MODEL_MATCH(87, knl_uncore_init),	/* Knights Landing */
-	X86_UNCORE_MODEL_MATCH(94, skl_uncore_init),	/* SkyLake */
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_NEHALEM_EP,	  nhm_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_NEHALEM,	  nhm_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_WESTMERE,	  nhm_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_WESTMERE_EP,	  nhm_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_SANDYBRIDGE,	  snb_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_IVYBRIDGE,	  ivb_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_CORE,	  hsw_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_ULT,	  hsw_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_GT3E,	  hsw_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_CORE_M, bdw_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_GT3E,	  bdw_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_SANDYBRIDGE_X,	  snbep_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_NEHALEM_EX,	  nhmex_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_WESTMERE_EX,	  nhmex_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_IVYBRIDGE_X,	  ivbep_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_HASWELL_X,	  hswep_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_X,	  bdx_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_BROADWELL_XEON_D, bdx_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_XEON_PHI_KNL,	  knl_uncore_init),
+	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP,  skl_uncore_init),
 	{},
 };
 
_

[PATCH 12/20] x86, edac: use Intel family name macros for edac driver

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Doug Thompson <dougthompson@xmission.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac@vger.kernel.org
---

 b/drivers/edac/sb_edac.c |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff -puN drivers/edac/sb_edac.c~x86-intel-familites-edac drivers/edac/sb_edac.c
--- a/drivers/edac/sb_edac.c~x86-intel-familites-edac	2016-06-01 15:45:07.657102586 -0700
+++ b/drivers/edac/sb_edac.c	2016-06-01 15:45:07.661102769 -0700
@@ -23,6 +23,7 @@
 #include <linux/math64.h>
 #include <linux/mod_devicetable.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/processor.h>
 #include <asm/mce.h>
 
@@ -3359,11 +3360,11 @@ fail0:
 
 /* Order here must match "enum type" */
 static const struct x86_cpu_id sbridge_cpuids[] = {
-	ICPU(0x2d, pci_dev_descr_sbridge_table),	/* SANDY_BRIDGE */
-	ICPU(0x3e, pci_dev_descr_ibridge_table),	/* IVY_BRIDGE */
-	ICPU(0x3f, pci_dev_descr_haswell_table),	/* HASWELL */
-	ICPU(0x4f, pci_dev_descr_broadwell_table),	/* BROADWELL */
-	ICPU(0x57, pci_dev_descr_knl_table),		/* KNIGHTS_LANDING */
+	ICPU(INTEL_FAM6_MODEL_SANDYBRIDGE_X,	pci_dev_descr_sbridge_table),
+	ICPU(INTEL_FAM6_MODEL_IVYBRIDGE_X,	pci_dev_descr_ibridge_table),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_X,	pci_dev_descr_haswell_table),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_X,	pci_dev_descr_broadwell_table),
+	ICPU(INTEL_FAM6_MODEL_XEON_PHI_KNL,	pci_dev_descr_knl_table),
 	{ }
 };
 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
_

[PATCH 13/20] x86, cpufreq: use Intel family name macros for intel_pstate cpufreq driver

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Len Brown <lenb@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
---

 b/drivers/cpufreq/intel_pstate.c |   37 +++++++++++++++++++------------------
 1 file changed, 19 insertions(+), 18 deletions(-)

diff -puN drivers/cpufreq/intel_pstate.c~x86-intel-families-cpufreq-pstate drivers/cpufreq/intel_pstate.c
--- a/drivers/cpufreq/intel_pstate.c~x86-intel-families-cpufreq-pstate	2016-06-01 15:45:08.102122880 -0700
+++ b/drivers/cpufreq/intel_pstate.c	2016-06-01 15:45:08.106123062 -0700
@@ -35,6 +35,7 @@
 #include <asm/msr.h>
 #include <asm/cpu_device_id.h>
 #include <asm/cpufeature.h>
+#include <asm/intel-family.h>
 
 #define ATOM_RATIOS		0x66a
 #define ATOM_VIDS		0x66b
@@ -1352,29 +1353,29 @@ static void intel_pstate_update_util(str
 			(unsigned long)&policy }
 
 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
-	ICPU(0x2a, core_params),
-	ICPU(0x2d, core_params),
-	ICPU(0x37, silvermont_params),
-	ICPU(0x3a, core_params),
-	ICPU(0x3c, core_params),
-	ICPU(0x3d, core_params),
-	ICPU(0x3e, core_params),
-	ICPU(0x3f, core_params),
-	ICPU(0x45, core_params),
-	ICPU(0x46, core_params),
-	ICPU(0x47, core_params),
-	ICPU(0x4c, airmont_params),
-	ICPU(0x4e, core_params),
-	ICPU(0x4f, core_params),
-	ICPU(0x5e, core_params),
-	ICPU(0x56, core_params),
-	ICPU(0x57, knl_params),
+	ICPU(INTEL_FAM6_MODEL_SANDYBRIDGE, core_params),
+	ICPU(INTEL_FAM6_MODEL_SANDYBRIDGE_X, core_params),
+	ICPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1, silvermont_params),
+	ICPU(INTEL_FAM6_MODEL_IVYBRIDGE, core_params),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_CORE, core_params),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_CORE_M, core_params),
+	ICPU(INTEL_FAM6_MODEL_IVYBRIDGE_X, core_params),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_X, core_params),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_ULT, core_params),
+	ICPU(INTEL_FAM6_MODEL_HASWELL_GT3E, core_params),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_GT3E, core_params),
+	ICPU(INTEL_FAM6_MODEL_ATOM_AIRMONT, airmont_params),
+	ICPU(INTEL_FAM6_MODEL_SKYLAKE_MOBILE, core_params),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_X, core_params),
+	ICPU(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, core_params),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_XEON_D, core_params),
+	ICPU(INTEL_FAM6_MODEL_XEON_PHI_KNL, knl_params),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
 
 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
-	ICPU(0x56, core_params),
+	ICPU(INTEL_FAM6_MODEL_BROADWELL_XEON_D, core_params),
 	{}
 };
 
_

[PATCH 14/20] x86, acpi, lss: use Intel family name macros for lpss driver

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Len Brown <lenb@kernel.org>
Cc: linux-acpi@vger.kernel.org
---

 b/drivers/acpi/acpi_lpss.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff -puN drivers/acpi/acpi_lpss.c~x86-intel-families-lpss drivers/acpi/acpi_lpss.c
--- a/drivers/acpi/acpi_lpss.c~x86-intel-families-lpss	2016-06-01 15:45:08.536142672 -0700
+++ b/drivers/acpi/acpi_lpss.c	2016-06-01 15:45:08.541142900 -0700
@@ -29,6 +29,7 @@ ACPI_MODULE_NAME("acpi_lpss");
 #ifdef CONFIG_X86_INTEL_LPSS
 
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/iosf_mbi.h>
 #include <asm/pmc_atom.h>
 
@@ -229,8 +230,8 @@ static const struct lpss_device_desc bsw
 #define ICPU(model)	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 
 static const struct x86_cpu_id lpss_cpu_ids[] = {
-	ICPU(0x37),	/* Valleyview, Bay Trail */
-	ICPU(0x4c),	/* Braswell, Cherry Trail */
+	ICPU(INTEL_FAM6_MODEL_ATOM_SILVERMONT1),	/* Valleyview, Bay Trail */
+	ICPU(INTEL_FAM6_MODEL_ATOM_AIRMONT),	/* Braswell, Cherry Trail */
 	{}
 };
 
_

[PATCH 15/20] x86, intel_telemetry: use Intel family name macros for telemetry driver

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Souvik Kumar Chakravarty <souvik.k.chakravarty@intel.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: platform-driver-x86@vger.kernel.org
---

 b/drivers/platform/x86/intel_telemetry_debugfs.c |    3 ++-
 b/drivers/platform/x86/intel_telemetry_pltdrv.c  |    3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff -puN drivers/platform/x86/intel_telemetry_debugfs.c~x86-intel-families-telemetry drivers/platform/x86/intel_telemetry_debugfs.c
--- a/drivers/platform/x86/intel_telemetry_debugfs.c~x86-intel-families-telemetry	2016-06-01 15:45:08.962162099 -0700
+++ b/drivers/platform/x86/intel_telemetry_debugfs.c	2016-06-01 15:45:08.967162327 -0700
@@ -32,6 +32,7 @@
 #include <linux/suspend.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/intel_pmc_ipc.h>
 #include <asm/intel_punit_ipc.h>
 #include <asm/intel_telemetry.h>
@@ -331,7 +332,7 @@ static struct telemetry_debugfs_conf tel
 };
 
 static const struct x86_cpu_id telemetry_debugfs_cpu_ids[] = {
-	TELEM_DEBUGFS_CPU(0x5c, telem_apl_debugfs_conf),
+	TELEM_DEBUGFS_CPU(INTEL_FAM6_MODEL_ATOM_GOLDMONT, telem_apl_debugfs_conf),
 	{}
 };
 
diff -puN drivers/platform/x86/intel_telemetry_pltdrv.c~x86-intel-families-telemetry drivers/platform/x86/intel_telemetry_pltdrv.c
--- a/drivers/platform/x86/intel_telemetry_pltdrv.c~x86-intel-families-telemetry	2016-06-01 15:45:08.964162191 -0700
+++ b/drivers/platform/x86/intel_telemetry_pltdrv.c	2016-06-01 15:45:08.968162373 -0700
@@ -28,6 +28,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/intel_pmc_ipc.h>
 #include <asm/intel_punit_ipc.h>
 #include <asm/intel_telemetry.h>
@@ -163,7 +164,7 @@ static struct telemetry_plt_config telem
 };
 
 static const struct x86_cpu_id telemetry_cpu_ids[] = {
-	TELEM_CPU(0x5c, telem_apl_config),
+	TELEM_CPU(INTEL_FAM6_MODEL_ATOM_GOLDMONT, telem_apl_config),
 	{}
 };
 
_

[PATCH 16/20] x86, pmc_core: use Intel family name macros for pmc_core driver

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Vishwanath Somayaji <vishwanath.somayaji@intel.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: platform-driver-x86@vger.kernel.org
---

 b/drivers/platform/x86/intel_pmc_core.c |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff -puN drivers/platform/x86/intel_pmc_core.c~x86-intel-families-pmc_core drivers/platform/x86/intel_pmc_core.c
--- a/drivers/platform/x86/intel_pmc_core.c~x86-intel-families-pmc_core	2016-06-01 15:45:09.410182530 -0700
+++ b/drivers/platform/x86/intel_pmc_core.c	2016-06-01 15:45:09.413182667 -0700
@@ -26,6 +26,7 @@
 #include <linux/seq_file.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/pmc_core.h>
 
 #include "intel_pmc_core.h"
@@ -138,10 +139,10 @@ static inline void pmc_core_dbgfs_unregi
 #endif /* CONFIG_DEBUG_FS */
 
 static const struct x86_cpu_id intel_pmc_core_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x4e, X86_FEATURE_MWAIT,
-		(kernel_ulong_t)NULL}, /* Skylake CPUID Signature */
-	{ X86_VENDOR_INTEL, 6, 0x5e, X86_FEATURE_MWAIT,
-		(kernel_ulong_t)NULL}, /* Skylake CPUID Signature */
+	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_MODEL_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
+		(kernel_ulong_t)NULL},
+	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
+		(kernel_ulong_t)NULL},
 	{}
 };
 
_

[PATCH 17/20] x86, mmc: use Intel family name macros for mmc driver

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

Another straightforward replacement of magic numbers.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-mmc@vger.kernel.org
---

 b/drivers/mmc/host/sdhci-acpi.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff -puN drivers/mmc/host/sdhci-acpi.c~x86-intel-families-sdhci-acpi drivers/mmc/host/sdhci-acpi.c
--- a/drivers/mmc/host/sdhci-acpi.c~x86-intel-families-sdhci-acpi	2016-06-01 15:45:09.826201501 -0700
+++ b/drivers/mmc/host/sdhci-acpi.c	2016-06-01 15:45:09.830201683 -0700
@@ -43,6 +43,7 @@
 
 #ifdef CONFIG_X86
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include <asm/iosf_mbi.h>
 #endif
 
@@ -126,7 +127,7 @@ static const struct sdhci_acpi_chip sdhc
 static bool sdhci_acpi_byt(void)
 {
 	static const struct x86_cpu_id byt[] = {
-		{ X86_VENDOR_INTEL, 6, 0x37 },
+		{ X86_VENDOR_INTEL, 6, INTEL_FAM6_MODEL_ATOM_SILVERMONT1 },
 		{}
 	};
 
_

[PATCH 18/20] x86, thermal: clean up and fix cpu model detection for intel_soc_dts_thermal

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

The X86_FAMILY_ANY in here is bogus.  "BYT" and model 0x37 are
family-6 only.  Simplify the code while we are in here.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: linux-pm@vger.kernel.org
---

 b/drivers/thermal/intel_soc_dts_thermal.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff -puN drivers/thermal/intel_soc_dts_thermal.c~buggy-intel_soc_dts_thermal drivers/thermal/intel_soc_dts_thermal.c
--- a/drivers/thermal/intel_soc_dts_thermal.c~buggy-intel_soc_dts_thermal	2016-06-01 15:45:10.235220153 -0700
+++ b/drivers/thermal/intel_soc_dts_thermal.c	2016-06-01 15:45:10.239220335 -0700
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
 #include "intel_soc_dts_iosf.h"
 
 #define CRITICAL_OFFSET_FROM_TJ_MAX	5000
@@ -42,7 +43,8 @@ static irqreturn_t soc_irq_thread_fn(int
 }
 
 static const struct x86_cpu_id soc_thermal_ids[] = {
-	{ X86_VENDOR_INTEL, X86_FAMILY_ANY, 0x37, 0, BYT_SOC_DTS_APIC_IRQ},
+	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_MODEL_ATOM_SILVERMONT1,
+		0, BYT_SOC_DTS_APIC_IRQ},
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids);
_

[PATCH 19/20] x86, rapl: add Skylake server model detection

[Dave Hansen]

From: Jacob Pan <jacob.jun.pan@linux.intel.com>

SKX uses similar RAPL interface as Broadwell server.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
---

 b/arch/x86/events/intel/rapl.c |    1 +
 1 file changed, 1 insertion(+)

diff -puN arch/x86/events/intel/rapl.c~x86-intel-familites-rapl-skx arch/x86/events/intel/rapl.c
--- a/arch/x86/events/intel/rapl.c~x86-intel-familites-rapl-skx	2016-06-01 15:45:10.645238850 -0700
+++ b/arch/x86/events/intel/rapl.c	2016-06-01 15:45:10.650239079 -0700
@@ -807,6 +807,7 @@ static const struct x86_cpu_id rapl_cpu_
 
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_MOBILE, skl_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, skl_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_MODEL_SKYLAKE_X, hsx_rapl_init),
 	{},
 };
 
_

[PATCH 20/20] x86, powercap, rapl: add Skylake Server model number

[Dave Hansen]

From: Dave Hansen <dave.hansen@linux.intel.com>

SKX uses similar RAPL interface as Broadwell server according to
Jacob Pan.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> 
Cc: linux-pm@vger.kernel.org 
---

 b/drivers/powercap/intel_rapl.c |    1 +
 1 file changed, 1 insertion(+)

diff -puN drivers/powercap/intel_rapl.c~x86-intel-familites-powercap-rapl-add-skx drivers/powercap/intel_rapl.c
--- a/drivers/powercap/intel_rapl.c~x86-intel-familites-powercap-rapl-add-skx	2016-06-01 15:45:11.070258232 -0700
+++ b/drivers/powercap/intel_rapl.c	2016-06-01 15:45:11.075258460 -0700
@@ -1114,6 +1114,7 @@ static const struct x86_cpu_id rapl_ids[
 
 	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_MOBILE,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_MODEL_SKYLAKE_X,		rapl_defaults_hsw_server),
 	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_MOBILE,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_MODEL_KABYLAKE_DESKTOP,	rapl_defaults_core),
 
_

Re: [PATCH 17/20] x86, mmc: use Intel family name macros for mmc driver

[Adrian Hunter]

On 02/06/16 03:12, Dave Hansen wrote:
> 
> From: Dave Hansen <dave.hansen@linux.intel.com>
> 
> Another straightforward replacement of magic numbers.
> 
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: Adrian Hunter <adrian.hunter@intel.com>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: linux-mmc@vger.kernel.org


Acked-by: Adrian Hunter <adrian.hunter@intel.com>


> ---
> 
>  b/drivers/mmc/host/sdhci-acpi.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff -puN drivers/mmc/host/sdhci-acpi.c~x86-intel-families-sdhci-acpi drivers/mmc/host/sdhci-acpi.c
> --- a/drivers/mmc/host/sdhci-acpi.c~x86-intel-families-sdhci-acpi	2016-06-01 15:45:09.826201501 -0700
> +++ b/drivers/mmc/host/sdhci-acpi.c	2016-06-01 15:45:09.830201683 -0700
> @@ -43,6 +43,7 @@
>  
>  #ifdef CONFIG_X86
>  #include <asm/cpu_device_id.h>
> +#include <asm/intel-family.h>
>  #include <asm/iosf_mbi.h>
>  #endif
>  
> @@ -126,7 +127,7 @@ static const struct sdhci_acpi_chip sdhc
>  static bool sdhci_acpi_byt(void)
>  {
>  	static const struct x86_cpu_id byt[] = {
> -		{ X86_VENDOR_INTEL, 6, 0x37 },
> +		{ X86_VENDOR_INTEL, 6, INTEL_FAM6_MODEL_ATOM_SILVERMONT1 },
>  		{}
>  	};
>  
> _
> 

Re: [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers

[Borislav Petkov]

On Wed, Jun 01, 2016 at 05:11:57PM -0700, Dave Hansen wrote:
> +#define INTEL_FAM6_MODEL_CORE_YONAH		0x0E
> +#define INTEL_FAM6_MODEL_CORE2_MEROM		0x0F

That "MODEL_" part looks redundant too IMO - you could simply do

INTEL_FAM6_NEHALEM and
INTEL_FAM6_SKYLAKE_DESKTOP
...

and so on and it is still clear what it is.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

RE: [PATCH 12/20] x86, edac: use Intel family name macros for edac driver

[Luck, Tony]

>  Another straightforward replacement of magic numbers.

It would be if I hadn't forgotten that INTEL_FAM6_MODEL_BROADWELL_XEON_D had
a separate model number from the other Broadwell Xeons when I switched the driver
from PCI device lookup to cpu model number.

This needs to add an entry for BDX-DE (use the same table initializer). Probably as
a separate patch before/after this.

-Tony

[The name INTEL_FAM6_MODEL_BROADWELL_XEON_D is so long it will spoil the
line-up of this code ... +1 vote on Boris' suggestion to drop the "MODEL_" bit from all these
names]

RE: [PATCH 12/20] x86, edac: use Intel family name macros for edac driver

[Luck, Tony]

> This needs to add an entry for BDX-DE (use the same table initializer). Probably as
> a separate patch before/after this.

Oops ... a bit worse than that. I assumed that index into the array matches the
enum ... (with a comment!) ... having two entries for the same "type" would break
that. I'll have to add a type field to something.

If your patch is on a fast-track, then go ahead with it:

Acked-by: Tony Luck <tony.luck@intel.com>

I'll work on fixing the other mess independently

-Tony

Re: [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers

[Darren Hart]

On Wed, Jun 01, 2016 at 05:11:57PM -0700, Dave Hansen wrote:
> 
> From: Dave Hansen <dave.hansen@linux.intel.com>
> 
> If you are cc'd on this code, please check _your_ code vs. the
> model list in "intel-family.h".  Please make sure you have all
> the models listed that you intend to.
> 
> Problem:
> 
> We have a boatload of open-coded family-6 model numbers.  Half of
> them have these model numbers in hex and the other half in
> decimal.  This makes grepping for them tons of fun, if you were
> to try.
> 
> Solution:
> 
> Consolidate all the magic numbers.  Put all the definitions in
> one header.
> 
> The names here are closely derived from the comments describing
> the models from arch/x86/events/intel/core.c.  We could easily
> make them shorter by doing things like s/SANDYBRIDGE/SNB/, but
> they seemed fine even with the longer versions to me.
> 
> Do not take any of these names too literally, like "DESKTOP"
> or "MOBILE".  These are all colloquial names and not precise
> descriptions of everywhere a given model will show up.
> 
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: Adrian Hunter <adrian.hunter@intel.com>
> Cc: Andi Kleen <ak@linux.intel.com>
> Cc: Andy Lutomirski <luto@kernel.org>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: Darren Hart <dvhart@infradead.org>

For platform/drivers/x86:

Magic number to macro mapping verified.

Acked-by: Darren Hart <dvhart@linux.intel.com>

-- 
Darren Hart
Intel Open Source Technology Center

Re: [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers

[Rafael J. Wysocki]

On Thursday, June 02, 2016 08:57:15 AM Borislav Petkov wrote:
> On Wed, Jun 01, 2016 at 05:11:57PM -0700, Dave Hansen wrote:
> > +#define INTEL_FAM6_MODEL_CORE_YONAH		0x0E
> > +#define INTEL_FAM6_MODEL_CORE2_MEROM		0x0F
> 
> That "MODEL_" part looks redundant too IMO - you could simply do
> 
> INTEL_FAM6_NEHALEM and
> INTEL_FAM6_SKYLAKE_DESKTOP
> ...
> 
> and so on and it is still clear what it is.

I'm with you on that, but that's rather minor and the changes in this series
are generally fine by me, so Dave please feel free to add

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

to all of it.

Thanks,
Rafael

Re: [PATCH 17/20] x86, mmc: use Intel family name macros for mmc driver

[Ulf Hansson]

On 2 June 2016 at 02:12, Dave Hansen <dave@sr71.net> wrote:
>
> From: Dave Hansen <dave.hansen@linux.intel.com>
>
> Another straightforward replacement of magic numbers.
>
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: Adrian Hunter <adrian.hunter@intel.com>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: linux-mmc@vger.kernel.org

Acked-by: Ulf Hansson <ulf.hansson@linaro.org>

I assume you are going to queue this via the x86 tree or whatever tree
that makes sense!?

Kind regards
Uffe

> ---
>
>  b/drivers/mmc/host/sdhci-acpi.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff -puN drivers/mmc/host/sdhci-acpi.c~x86-intel-families-sdhci-acpi drivers/mmc/host/sdhci-acpi.c
> --- a/drivers/mmc/host/sdhci-acpi.c~x86-intel-families-sdhci-acpi       2016-06-01 15:45:09.826201501 -0700
> +++ b/drivers/mmc/host/sdhci-acpi.c     2016-06-01 15:45:09.830201683 -0700
> @@ -43,6 +43,7 @@
>
>  #ifdef CONFIG_X86
>  #include <asm/cpu_device_id.h>
> +#include <asm/intel-family.h>
>  #include <asm/iosf_mbi.h>
>  #endif
>
> @@ -126,7 +127,7 @@ static const struct sdhci_acpi_chip sdhc
>  static bool sdhci_acpi_byt(void)
>  {
>         static const struct x86_cpu_id byt[] = {
> -               { X86_VENDOR_INTEL, 6, 0x37 },
> +               { X86_VENDOR_INTEL, 6, INTEL_FAM6_MODEL_ATOM_SILVERMONT1 },
>                 {}
>         };
>
> _