From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161045AbcFCPel (ORCPT ); Fri, 3 Jun 2016 11:34:41 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57358 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752103AbcFCPej (ORCPT ); Fri, 3 Jun 2016 11:34:39 -0400 Date: Fri, 3 Jun 2016 17:34:33 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Haozhong Zhang Cc: kvm@vger.kernel.org, Paolo Bonzini , Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, Gleb Natapov , Boris Petkov , Tony Luck , Ashok Raj , Andi Kleen Subject: Re: [PATCH v1] KVM: VMX: enable guest access to LMCE related MSRs Message-ID: <20160603153433.GA20152@potion> References: <20160603060851.17018-1-haozhong.zhang@intel.com> <20160603060851.17018-2-haozhong.zhang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160603060851.17018-2-haozhong.zhang@intel.com> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 03 Jun 2016 15:34:38 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2016-06-03 14:08+0800, Haozhong Zhang: > On Intel platforms, this patch adds LMCE to KVM MCE supported > capabilities and handles guest access to LMCE related MSRs. > > Signed-off-by: Ashok Raj > Signed-off-by: Haozhong Zhang > --- > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > @@ -2863,6 +2863,11 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) > return 0; > } > > +static inline bool vmx_feature_control_msr_required(struct kvm_vcpu *vcpu) I'd call it "present", rather than "required". SDM does so for other MSRs and it is easier to understand in the condition that returns #GP if this function is false. > +{ > + return nested_vmx_allowed(vcpu) || (vcpu->arch.mcg_cap & MCG_LMCE_P); > +} > @@ -2904,8 +2909,15 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > case MSR_IA32_FEATURE_CONTROL: > - if (!nested_vmx_allowed(vcpu)) > + if (!vmx_feature_control_msr_required(vcpu)) > return 1; > msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control; (MSR_IA32_FEATURE_CONTROL does not depend only on nested anymore, so moving msr_ia32_feature_control from struct nested_vmx to struct vcpu_vmx would make sense.) > break; > @@ -2997,8 +3009,17 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > + case MSR_IA32_MCG_EXT_CTL: > + if (!(vcpu->arch.mcg_cap & MCG_LMCE_P) || > + !(to_vmx(vcpu)->nested.msr_ia32_feature_control & > + FEATURE_CONTROL_LMCE)) (This check is used twice and could be given a name too, "vmx_mcg_ext_ctl_msr_present()"?) > + return 1; > + if (data && data != 0x1) (data & ~MCG_EXT_CTL_LMCE_EN) is a clearer check for reserved bits. > + return -1; > + vcpu->arch.mcg_ext_ctl = data; > + break; > case MSR_IA32_FEATURE_CONTROL: > - if (!nested_vmx_allowed(vcpu) || > + if (!vmx_feature_control_msr_required(vcpu) || > (to_vmx(vcpu)->nested.msr_ia32_feature_control & > FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) > return 1; Does hardware throw #GP when FEATURE_CONTROL_LMCE is set without MCG_LMCE_P? (We could emulate that by having a mask of valid bits and also use that mask in place of vmx_feature_control_msr_required(). I don't think there is a reason to have only vmx_feature_control_msr_required() if the hardware can #GP on individual bits too.) Thanks.