From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754907AbcFHGsO (ORCPT ); Wed, 8 Jun 2016 02:48:14 -0400 Received: from merlin.infradead.org ([205.233.59.134]:57419 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754808AbcFHGsN (ORCPT ); Wed, 8 Jun 2016 02:48:13 -0400 Date: Wed, 8 Jun 2016 08:48:00 +0200 From: Peter Zijlstra To: Lukasz Odzioba Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, ak@linux.intel.com, kan.liang@intel.com, akpm@linux-foundation.org, eranian@google.com, acme@kernel.org, alexander.shishkin@linux.intel.com, bp@suse.de, lukasz.anaczkowski@intel.com Subject: Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing Message-ID: <20160608064800.GN30154@twins.programming.kicks-ass.net> References: <1465358536-21544-1-git-send-email-lukasz.odzioba@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1465358536-21544-1-git-send-email-lukasz.odzioba@intel.com> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 08, 2016 at 06:02:16AM +0200, Lukasz Odzioba wrote: > For Knights Landing processor we need to filter OFFCORE_RESPONSE > events by config1 parameter to make sure that it will end up in > an appropriate PMC to meet specification. > > On Knights Landing: > MSR_OFFCORE_RSP_1 bits 8, 11, 14 can be used only on PMC1 > MSR_OFFCORE_RSP_0 bit 38 can be used only on PMC0 > > This patch introduces INTEL_EEVENT_CONSTRAINT where third parameter > specifies extended config bits allowed only on given PMCs. > How does this work in the light of intel_alt_er() ?