From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1426128AbcFIEna (ORCPT ); Thu, 9 Jun 2016 00:43:30 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:24848 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751031AbcFIEn2 (ORCPT ); Thu, 9 Jun 2016 00:43:28 -0400 X-IBM-Helo: d23dlp02.au.ibm.com X-IBM-MailFrom: sam.bobroff@au1.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org Date: Thu, 9 Jun 2016 14:42:25 +1000 From: Sam Bobroff To: "Shreyas B. Prabhu" Cc: mpe@ellerman.id.au, ego@linux.vnet.ibm.com, mikey@neuling.org, maddy@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction References: <1464871141-11568-1-git-send-email-shreyas@linux.vnet.ibm.com> <1464871141-11568-9-git-send-email-shreyas@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1464871141-11568-9-git-send-email-shreyas@linux.vnet.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16060904-0012-0000-0000-0000019D1B85 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16060904-0013-0000-0000-0000055D3D64 Message-Id: <20160609044225.GA16550@tungsten.ozlabs.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-06-08_11:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1606090047 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 02, 2016 at 07:38:58AM -0500, Shreyas B. Prabhu wrote: ... > +/* Power Management - PSSCR Fields */ It might be nice to give the full name of the register, as below with the FPSCR. > +#define PSSCR_RL_MASK 0x0000000F > +#define PSSCR_MTL_MASK 0x000000F0 > +#define PSSCR_TR_MASK 0x00000300 > +#define PSSCR_PSLL_MASK 0x000F0000 > +#define PSSCR_EC 0x00100000 > +#define PSSCR_ESL 0x00200000 > +#define PSSCR_SD 0x00400000 > + > + > /* Floating Point Status and Control Register (FPSCR) Fields */ Cheers, Sam.