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Date: Thu, 9 Jun 2016 21:25:16 +0800
From: Shawn Guo <shawnguo@kernel.org>
To: Damien Riegel <damien.riegel@savoirfairelinux.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        Mark Rutland <mark.rutland@arm.com>, Pawel Moll <pawel.moll@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Russell King <linux@armlinux.org.uk>, Rob Herring <robh+dt@kernel.org>,
        kernel@savoirfairelinux.com, Sascha Hauer <kernel@pengutronix.de>,
        Kumar Gala <galak@codeaurora.org>
Subject: Re: [PATCH 1/2] ARM: dts: TS-4800: add FPGA's IRQ controller support
Message-ID: <20160609132516.GA19473@tiger>
References: <1463516190-10606-1-git-send-email-damien.riegel@savoirfairelinux.com>
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On Tue, May 17, 2016 at 04:16:29PM -0400, Damien Riegel wrote:
> Enable FPGA's IRQ controller. It is in charge of dispatching interrupts
> generated by IPs in the FPGA. The SoC is notified that an interrupt
> occurred through a GPIO.
> 
> Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
> ---
>  arch/arm/boot/dts/imx51-ts4800.dts | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
> index 0ff76a1..2c89988 100644
> --- a/arch/arm/boot/dts/imx51-ts4800.dts
> +++ b/arch/arm/boot/dts/imx51-ts4800.dts
> @@ -149,6 +149,19 @@
>  		#size-cells = <1>;
>  		ranges = <0 0 0 0x1d000>;
>  
> +		fpga_irqc: fpga_irqc@0,15000 {

Please use hyphen rather than underscore in node name.  Also
why do we need '0,' in unit-address?

> +			compatible = "technologic,ts4800-irqc";
> +			reg = <0x15000 0x1000>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&pinctrl_interrupt_fpga>;
> +

Drop this newline.

> +			interrupt-parent = <&gpio2>;
> +			interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
> +

Ditto

Shawn

> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +		};
> +
>  		syscon: syscon@b0010000 {
>  			compatible = "syscon", "simple-mfd";
>  			reg = <0x10000 0x3d>;
> @@ -228,6 +241,12 @@
>  		>;
>  	};
>  
> +	pinctrl_interrupt_fpga: fpgaicgrp {
> +		fsl,pins = <
> +			MX51_PAD_EIM_D27__GPIO2_9		0xe5
> +		>;
> +	};
> +
>  	pinctrl_lcd: lcdgrp {
>  		fsl,pins = <
>  			MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
> -- 
> 2.5.0
> 
> 
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