From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933417AbcFJQOV (ORCPT ); Fri, 10 Jun 2016 12:14:21 -0400 Received: from mail.csclub.uwaterloo.ca ([129.97.134.52]:44885 "EHLO mail.csclub.uwaterloo.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933279AbcFJQOS (ORCPT ); Fri, 10 Jun 2016 12:14:18 -0400 X-Greylist: delayed 474 seconds by postgrey-1.27 at vger.kernel.org; Fri, 10 Jun 2016 12:14:18 EDT From: "Lennart Sorensen" Date: Fri, 10 Jun 2016 12:06:21 -0400 To: Sebastian Frias Cc: Thomas Gleixner , Marc Zyngier , LKML , Grygorii Strashko , Sricharan R , Mason , =?utf-8?B?TcOlbnMgUnVsbGfDpXJk?= Subject: Re: Using irq-crossbar.c Message-ID: <20160610160621.GA5829@csclub.uwaterloo.ca> References: <575ADEBA.2030202@laposte.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <575ADEBA.2030202@laposte.net> User-Agent: Mutt/1.5.23 (2014-03-12) X-Spam-Flag: NO Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 10, 2016 at 05:37:30PM +0200, Sebastian Frias wrote: > We are trying to write a driver for an interrupt controller (actually more of a crossbar) for an ARM-based SoC. > This IRQ crossbar has 128 inputs and 24 outputs, the outputs are connected directly to the GIC. > The idea is that the GIC handles everything, and just request a mapping from an IRQ number (0...127, from a device's DT entry) into one of its 24 input lines. > > By looking at current code (4.7-rc1) there seems to be a driver (drivers/irqchip/irq-crossbar.c) that provides similar functionality. > The driver uses hierarchical irq domains (since commit 783d31863fb8 "irqchip: crossbar: Convert dra7 crossbar to stacked domains") which we believe we don't need because the only controller is the GIC. > However the API used previously, register_routable_domain_ops(), was removed with commit a5561c3e845c "irqchip: gic: Get rid of routable domain". > > Trying to use the driver with hierarchical domains (after modifications for our SoC), results on the kernel being blocked at some point: > > [ 0.041524] ThumbEE CPU extension supported. > [ 0.041589] Registering SWP/SWPB emulation handler > [ 0.052022] Freeing unused kernel memory: 12364K (c029b000 - c0eae000) > [ 0.074084] random: dbus-uuidgen urandom read with 0 bits of entropy available > > We've put logs on the different domain_ops calls (alloc, free, translate) but they are not called, even if the DT is supposed to tell devices to take interrupts from this controller (*). > > Do you have suggestions on what APIs should be used, further reading/examples and/or pointers on how debug this (logs to enable, things to look for, etc.)? Well irq-crossbar.c seems to be very specific to the crossbar in TI chips which handle lots of inputs and lots of outputs to multiple receivers (not just the GIC) as far as I have understood it. Also, unless you modified the IRQCHIP_DECLARE at the end, I see nothing in your dtb that would match the driver at all. And even if that did match, is your crossbar at all register compatible with the TI design? irq-crossbar might be a good example for how to write such a driver, but I wouldn't have much hope of it being useful as a generic driver, never mind the unfortunate name the source file has. I suspect ti-irq-crossbar.c would have been much more appropriate. -- Len Soremsem