From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424796AbcFMPm1 (ORCPT ); Mon, 13 Jun 2016 11:42:27 -0400 Received: from mail.csclub.uwaterloo.ca ([129.97.134.52]:40234 "EHLO mail.csclub.uwaterloo.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423688AbcFMPm0 (ORCPT ); Mon, 13 Jun 2016 11:42:26 -0400 From: "Lennart Sorensen" Date: Mon, 13 Jun 2016 11:42:23 -0400 To: Sebastian Frias Cc: Mason , Marc Zyngier , Thomas Gleixner , LKML , Grygorii Strashko , Mans Rullgard Subject: Re: Using irq-crossbar.c Message-ID: <20160613154223.GP5827@csclub.uwaterloo.ca> References: <575ADEBA.2030202@laposte.net> <575AE52E.9020005@arm.com> <575B16BD.50600@free.fr> <20160611105840.69324f8e@arm.com> <575C304F.2070303@free.fr> <20160613140405.GB5829@csclub.uwaterloo.ca> <575EC9C9.3040201@laposte.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <575EC9C9.3040201@laposte.net> User-Agent: Mutt/1.5.23 (2014-03-12) X-Spam-Flag: NO Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 13, 2016 at 04:57:13PM +0200, Sebastian Frias wrote: > Actually we have 128 inputs and 24 outputs, the 24 outputs go straight to the GIC. > The HW block is a many-to-many router. > There are 128 32bit registers which specify, for each of the corresponding 128 inputs, to which of the 24 outputs it would be routed to. > > There are 4 32bit registers that can show the RAW status of the 128 inputs, but they do not latch on the inputs. > That's why our understanding is that on Linux terms it is not an interrupt controller, but just a many-to-many mux, the only real interrupt-controller (where one can set if the line is active high or low for example) is the GIC. Well that does just sound like a mux. But that does mean you either can't use more than 24 inputs at once, or you will be sharing interrupts. I really hate shared interrutps so I would never design something that way, but it is simpler. > Thanks for the background on the i8259 and the cascaded interrupts. > However, our understanding is that it would only be required if more than 24 devices request IRQ lines, in which case, some of them would have to share a single GIC IRQ line, right? > Shall we worry about that now? Well if you are sure you never need more than 24 devices registered at once, then it shouldn't be a problem. > This is interesting. > We have one interrupt controller already upstream, drivers/irqchip/irq-tango.c, and our understanding is that it dispatches one IRQ at the time, see tangox_dispatch_irqs() function, is that what you are discussing? That does look like a proper interrupt controller that could be cascaded of another one if needed. -- Len Sorensen