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* [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1
@ 2016-06-14  3:01 Masahiro Yamada
  2016-06-14  3:01 ` [PATCH 1/3] arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs Masahiro Yamada
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Masahiro Yamada @ 2016-06-14  3:01 UTC (permalink / raw)
  To: arm
  Cc: Masahiro Yamada, Will Deacon, Catalin Marinas, linux-arm-kernel,
	linux-kernel



Masahiro Yamada (3):
  arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
  arm64: dts: uniphier: change cpu-release-address
  arm64: dts: uniphier: add /memreserve/ for spin-table release address

 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

-- 
1.9.1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/3] arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
  2016-06-14  3:01 [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Masahiro Yamada
@ 2016-06-14  3:01 ` Masahiro Yamada
  2016-06-14  3:01 ` [PATCH 2/3] arm64: dts: uniphier: change cpu-release-address Masahiro Yamada
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2016-06-14  3:01 UTC (permalink / raw)
  To: arm
  Cc: Masahiro Yamada, Will Deacon, Catalin Marinas, linux-arm-kernel,
	linux-kernel

This node consists of various system-level configuration registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index 9532880..31dc51b 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -264,9 +264,13 @@
 			reg = <0x59801000 0x400>;
 		};
 
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-ld20-pinctrl", "syscon";
-			reg = <0x5f801000 0xe00>;
+		soc-glue@5f800000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+
+			pinctrl: pinctrl {
+				 compatible = "socionext,uniphier-ld20-pinctrl";
+			};
 		};
 
 		gic: interrupt-controller@5fe00000 {
-- 
1.9.1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/3] arm64: dts: uniphier: change cpu-release-address
  2016-06-14  3:01 [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Masahiro Yamada
  2016-06-14  3:01 ` [PATCH 1/3] arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs Masahiro Yamada
@ 2016-06-14  3:01 ` Masahiro Yamada
  2016-06-14  3:01 ` [PATCH 3/3] arm64: dts: uniphier: add /memreserve/ for spin-table release address Masahiro Yamada
  2016-06-14 17:41 ` [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Olof Johansson
  3 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2016-06-14  3:01 UTC (permalink / raw)
  To: arm
  Cc: Masahiro Yamada, Will Deacon, Catalin Marinas, linux-arm-kernel,
	linux-kernel

At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index 31dc51b..644025c 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -77,7 +77,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
 		cpu1: cpu@1 {
@@ -85,7 +85,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
 		cpu2: cpu@100 {
@@ -93,7 +93,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
 		cpu3: cpu@101 {
@@ -101,7 +101,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 	};
 
-- 
1.9.1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 3/3] arm64: dts: uniphier: add /memreserve/ for spin-table release address
  2016-06-14  3:01 [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Masahiro Yamada
  2016-06-14  3:01 ` [PATCH 1/3] arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs Masahiro Yamada
  2016-06-14  3:01 ` [PATCH 2/3] arm64: dts: uniphier: change cpu-release-address Masahiro Yamada
@ 2016-06-14  3:01 ` Masahiro Yamada
  2016-06-14 17:41 ` [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Olof Johansson
  3 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2016-06-14  3:01 UTC (permalink / raw)
  To: arm
  Cc: Masahiro Yamada, Will Deacon, Catalin Marinas, linux-arm-kernel,
	linux-kernel

As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index 644025c..c223915 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -42,6 +42,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+
 / {
 	compatible = "socionext,ph1-ld20";
 	#address-cells = <2>;
-- 
1.9.1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1
  2016-06-14  3:01 [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Masahiro Yamada
                   ` (2 preceding siblings ...)
  2016-06-14  3:01 ` [PATCH 3/3] arm64: dts: uniphier: add /memreserve/ for spin-table release address Masahiro Yamada
@ 2016-06-14 17:41 ` Olof Johansson
  3 siblings, 0 replies; 5+ messages in thread
From: Olof Johansson @ 2016-06-14 17:41 UTC (permalink / raw)
  To: Masahiro Yamada
  Cc: arm, Will Deacon, Catalin Marinas, linux-arm-kernel, linux-kernel

On Tue, Jun 14, 2016 at 12:01:40PM +0900, Masahiro Yamada wrote:
> 
> 
> Masahiro Yamada (3):
>   arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
>   arm64: dts: uniphier: change cpu-release-address
>   arm64: dts: uniphier: add /memreserve/ for spin-table release address

Applied, thanks.


-Olof

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2016-06-14 17:48 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2016-06-14  3:01 [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Masahiro Yamada
2016-06-14  3:01 ` [PATCH 1/3] arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs Masahiro Yamada
2016-06-14  3:01 ` [PATCH 2/3] arm64: dts: uniphier: change cpu-release-address Masahiro Yamada
2016-06-14  3:01 ` [PATCH 3/3] arm64: dts: uniphier: add /memreserve/ for spin-table release address Masahiro Yamada
2016-06-14 17:41 ` [PATCH 0/3] arm64: dts: uniphier: UniPhier DTS updates (64bit) for v4.8-rc1 Olof Johansson

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