From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755734AbcFQPpk (ORCPT ); Fri, 17 Jun 2016 11:45:40 -0400 Received: from foss.arm.com ([217.140.101.70]:51391 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932315AbcFQPpg (ORCPT ); Fri, 17 Jun 2016 11:45:36 -0400 Date: Fri, 17 Jun 2016 16:45:36 +0100 From: Will Deacon To: Waiman Long Cc: Boqun Feng , Peter Zijlstra , Ingo Molnar , linux-kernel@vger.kernel.org, x86@kernel.org, linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-s390@vger.kernel.org, linux-arch@vger.kernel.org, Davidlohr Bueso , Jason Low , Dave Chinner , Scott J Norton , Douglas Hatch Subject: Re: [RFC PATCH-tip v2 1/6] locking/osq: Make lock/unlock proper acquire/release barrier Message-ID: <20160617154536.GB1284@arm.com> References: <1465944489-43440-1-git-send-email-Waiman.Long@hpe.com> <1465944489-43440-2-git-send-email-Waiman.Long@hpe.com> <20160615080446.GA28443@insomnia> <5761A5FF.5070703@hpe.com> <20160616021951.GA16918@insomnia> <57631BBA.9070505@hpe.com> <20160617004837.GB16918@insomnia> <576416B1.6020006@hpe.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <576416B1.6020006@hpe.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 17, 2016 at 11:26:41AM -0400, Waiman Long wrote: > On 06/16/2016 08:48 PM, Boqun Feng wrote: > >On Thu, Jun 16, 2016 at 05:35:54PM -0400, Waiman Long wrote: > >>If you look into the actual code: > >> > >> next = xchg_release(&node->next, NULL); > >> if (next) { > >> WRITE_ONCE(next->locked, 1); > >> return; > >> } > >> > >>There is a control dependency that WRITE_ONCE() won't happen until > >But a control dependency only orders LOAD->STORE pairs, right? And here > >the control dependency orders the LOAD part of xchg_release() and the > >WRITE_ONCE(). > > > >Along with the fact that RELEASE only orders the STORE part of xchg with > >the memory operations preceding the STORE part, so for the following > >code: > > > > WRTIE_ONCE(x,1); > > next = xchg_release(&node->next, NULL); > > if (next) > > WRITE_ONCE(next->locked, 1); > > > >such a reordering is allowed to happen on ARM64v8 > > > > next = ldxr [&node->next] // LOAD part of xchg_release() > > > > if (next) > > WRITE_ONCE(next->locked, 1); > > > > WRITE_ONCE(x,1); > > stlxr NULL [&node->next] // STORE part of xchg_releae() > > > >Am I missing your point here? > > My understanding of the release barrier is that both prior LOADs and STOREs > can't move after the barrier. If WRITE_ONCE(x, 1) can move to below as shown > above, it is not a real release barrier and we may need to change the > barrier code. You seem to be missing the point. {READ,WRITE}_ONCE accesses appearing in program order after a release are not externally ordered with respect to the release unless they access the same location. This is illustrated by Boqun's example, which shows two WRITE_ONCE accesses being reordered before a store-release forming the write component of an xchg_release. In both cases, WRITE_ONCE(x, 1) remains ordered before the store-release. Will