From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754322AbcFTJ5Z (ORCPT ); Mon, 20 Jun 2016 05:57:25 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:36965 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752729AbcFTJ5Q (ORCPT ); Mon, 20 Jun 2016 05:57:16 -0400 Date: Mon, 20 Jun 2016 10:57:01 +0100 From: Lee Jones To: Peter Ujfalusi Cc: linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, tony@atomide.com, devicetree@vger.kernel.org Subject: Re: [PATCH] mfd: twl6040: Handle mclk used for HPPLL and optional internal clock source Message-ID: <20160620095701.GF1465@dell> References: <1462965209-6955-1-git-send-email-peter.ujfalusi@ti.com> <20160616151658.GA21702@dell> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 20 Jun 2016, Peter Ujfalusi wrote: > On 06/16/2016 06:16 PM, Lee Jones wrote: > > On Wed, 11 May 2016, Peter Ujfalusi wrote: > > > >> On some boards, like omap5-uevm the MCLK is gated by default and in order > >> to be able to use the High performance modes of twl6040 it need to be > >> enabled by SW. > >> Add support for handling the MCLK source clock via CCF. > >> At the same time lover the print priority of the notification that the 32K > > > > Mr Lover Lover! > > Oh. :D > > >> twl6040->supplies[0].supply = "vio"; > >> diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h > >> index 8f9fc3d26e6d..a7c50e54f3e0 100644 > >> --- a/include/linux/mfd/twl6040.h > >> +++ b/include/linux/mfd/twl6040.h > >> @@ -224,7 +224,8 @@ struct twl6040 { > >> struct regmap *regmap; > >> struct regmap_irq_chip_data *irq_data; > >> struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ > >> - struct clk *clk32k; > >> + struct clk *clk32k_clk; > >> + struct clk *mclk_clk; > > > > Not sure I get the naming here. > > > > What's wrong with clk32k and mclk? > > The struct already have mclk (unsigned int) member to store the rate of the > reference clock (32768 in case of LPPLL or the rate of the mclk clock in case > of HPPLL). I could use clk32k and mclk for the clk and rename the current mclk > to refclk_rate or something if that is better. This value is only important > for the HPPLL usage, if I restructure the driver I might be able to rename it > as mclk_rate and store only the MCLK freq there. That would be less ambiguous, yes. > >> struct mutex mutex; > >> struct mutex irq_mutex; > >> struct mfd_cell cells[TWL6040_CELLS]; > > > > -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog