[PATCH v2 0/3] Exynos big-endian fixes

[PATCH v2 0/3] Exynos big-endian fixes

[Matthew Leach]

Hi all,

I believe these are the outstanding patches from my Exynos big-endian
series that haven't yet been merged.  If I've missed anything, please
let me know.

Comments welcome,
Matt

v1 -> v2:
  - Fixed white-space issues.
  - Used readb_relaxed in tty driver for completeness.

Matthew Leach (3):
  irqchip: exynos_combiner: fixup reg access on be
  tty: serial: samsung: fixup accessors for endian
  tty: serial: samsung: add byte-order aware bit functions

 drivers/irqchip/exynos-combiner.c | 18 +++++++++---------
 drivers/tty/serial/samsung.c      | 16 +++++++---------
 drivers/tty/serial/samsung.h      | 38 +++++++++++++++++++++++++++++++++-----
 3 files changed, 49 insertions(+), 23 deletions(-)

-- 
2.8.3

[PATCH v2 1/3] irqchip: exynos_combiner: fixup reg access on be

[Matthew Leach]

Use the byte-order aware big endian accessors, allowing for kernels
running under big-endian.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Jason Cooper <jason@lakedaemon.net>
CC: Marc Zyngier <marc.zyngier@arm.com>
CC: Kukjin Kim <kgene@kernel.org>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-samsung-soc@vger.kernel.org
---
 drivers/irqchip/exynos-combiner.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index ead15be..97ae34c 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
 {
 	u32 mask = 1 << (data->hwirq % 32);
 
-	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
 	u32 mask = 1 << (data->hwirq % 32);
 
-	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
 
 static void combiner_handle_cascade_irq(struct irq_desc *desc)
@@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 
 	spin_lock(&irq_controller_lock);
-	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+	status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
 	spin_unlock(&irq_controller_lock);
 	status &= chip_data->irq_mask;
 
@@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
 	combiner_data->parent_irq = irq;
 
 	/* Disable all interrupts */
-	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
+	writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
 }
 
 static int combiner_irq_domain_xlate(struct irq_domain *d,
@@ -218,7 +218,7 @@ static int combiner_suspend(void)
 
 	for (i = 0; i < max_nr; i++)
 		combiner_data[i].pm_save =
-			__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
+			readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
 
 	return 0;
 }
@@ -235,10 +235,10 @@ static void combiner_resume(void)
 	int i;
 
 	for (i = 0; i < max_nr; i++) {
-		__raw_writel(combiner_data[i].irq_mask,
-			     combiner_data[i].base + COMBINER_ENABLE_CLEAR);
-		__raw_writel(combiner_data[i].pm_save,
-			     combiner_data[i].base + COMBINER_ENABLE_SET);
+		writel_relaxed(combiner_data[i].irq_mask,
+			       combiner_data[i].base + COMBINER_ENABLE_CLEAR);
+		writel_relaxed(combiner_data[i].pm_save,
+			       combiner_data[i].base + COMBINER_ENABLE_SET);
 	}
 }
 
-- 
2.8.3

[PATCH v2 2/3] tty: serial: samsung: fixup accessors for endian

[Matthew Leach]

Fix the serial access code to deal with kernels built for big endian
operation.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
Acked-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Jiri Slaby <jslaby@suse.com>
CC: linux-serial@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 drivers/tty/serial/samsung.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index fc5deaa..8f96b71 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -117,10 +117,10 @@ struct s3c24xx_uart_port {
 #define portaddrl(port, reg) \
 	((unsigned long *)(unsigned long)((port)->membase + (reg)))
 
-#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
-#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
+#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
+#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 
-#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
-#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
+#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
+#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 
 #endif
-- 
2.8.3

[PATCH v2 3/3] tty: serial: samsung: add byte-order aware bit functions

[Matthew Leach]

This driver makes use of the __set_bit() and __clear_bit() functions.
When running under big-endian, these functions don't convert the bit
indexes when working with peripheral registers, leading to the
incorrect bits being set and cleared when running big-endian.

Add two new driver functions for setting and clearing bits that are
byte-order aware.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Jiri Slaby <jslaby@suse.com>
CC: linux-serial@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 drivers/tty/serial/samsung.c | 16 +++++++---------
 drivers/tty/serial/samsung.h | 28 ++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 99bb231..e4f53d5 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -169,8 +169,7 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
 		return;
 
 	if (s3c24xx_serial_has_interrupt_mask(port))
-		__set_bit(S3C64XX_UINTM_TXD,
-			portaddrl(port, S3C64XX_UINTM));
+		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 	else
 		disable_irq_nosync(ourport->tx_irq);
 
@@ -235,8 +234,7 @@ static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 
 	/* Mask Tx interrupt */
 	if (s3c24xx_serial_has_interrupt_mask(port))
-		__set_bit(S3C64XX_UINTM_TXD,
-			  portaddrl(port, S3C64XX_UINTM));
+		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 	else
 		disable_irq_nosync(ourport->tx_irq);
 
@@ -269,8 +267,8 @@ static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 
 	/* Unmask Tx interrupt */
 	if (s3c24xx_serial_has_interrupt_mask(port))
-		__clear_bit(S3C64XX_UINTM_TXD,
-			    portaddrl(port, S3C64XX_UINTM));
+		s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
+				  S3C64XX_UINTM);
 	else
 		enable_irq(ourport->tx_irq);
 
@@ -397,8 +395,8 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
 	if (rx_enabled(port)) {
 		dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 		if (s3c24xx_serial_has_interrupt_mask(port))
-			__set_bit(S3C64XX_UINTM_RXD,
-				portaddrl(port, S3C64XX_UINTM));
+			s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
+					S3C64XX_UINTM);
 		else
 			disable_irq_nosync(ourport->rx_irq);
 		rx_enabled(port) = 0;
@@ -1069,7 +1067,7 @@ static int s3c64xx_serial_startup(struct uart_port *port)
 	spin_unlock_irqrestore(&port->lock, flags);
 
 	/* Enable Rx Interrupt */
-	__clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
+	s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
 
 	dbg("s3c64xx_serial_startup ok\n");
 	return ret;
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 8f96b71..2ae4fce 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -123,4 +123,32 @@ struct s3c24xx_uart_port {
 #define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 
+/* Byte-order aware bit setting/clearing functions. */
+
+static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
+				   unsigned int reg)
+{
+	unsigned long flags;
+	u32 val;
+
+	local_irq_save(flags);
+	val = rd_regl(port, reg);
+	val |= (1 << idx);
+	wr_regl(port, reg, val);
+	local_irq_restore(flags);
+}
+
+static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
+				     unsigned int reg)
+{
+	unsigned long flags;
+	u32 val;
+
+	local_irq_save(flags);
+	val = rd_regl(port, reg);
+	val &= ~(1 << idx);
+	wr_regl(port, reg, val);
+	local_irq_restore(flags);
+}
+
 #endif
-- 
2.8.3

Re: [PATCH v2 1/3] irqchip: exynos_combiner: fixup reg access on be

[Jason Cooper]

Matt, Ben,

Both of you submitted similar patches for the same driver, same purpose.
Since Ben's hit my inbox first, I'll take his.

thx,

Jason.

On Wed, Jun 22, 2016 at 05:57:01PM +0100, Matthew Leach wrote:
> Use the byte-order aware big endian accessors, allowing for kernels
> running under big-endian.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Jason Cooper <jason@lakedaemon.net>
> CC: Marc Zyngier <marc.zyngier@arm.com>
> CC: Kukjin Kim <kgene@kernel.org>
> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> CC: linux-kernel@vger.kernel.org
> CC: linux-arm-kernel@lists.infradead.org
> CC: linux-samsung-soc@vger.kernel.org
> ---
>  drivers/irqchip/exynos-combiner.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
> index ead15be..97ae34c 100644
> --- a/drivers/irqchip/exynos-combiner.c
> +++ b/drivers/irqchip/exynos-combiner.c
> @@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
>  {
>  	u32 mask = 1 << (data->hwirq % 32);
>  
> -	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
> +	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
>  }
>  
>  static void combiner_unmask_irq(struct irq_data *data)
>  {
>  	u32 mask = 1 << (data->hwirq % 32);
>  
> -	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
> +	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
>  }
>  
>  static void combiner_handle_cascade_irq(struct irq_desc *desc)
> @@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
>  	chained_irq_enter(chip, desc);
>  
>  	spin_lock(&irq_controller_lock);
> -	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
> +	status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
>  	spin_unlock(&irq_controller_lock);
>  	status &= chip_data->irq_mask;
>  
> @@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
>  	combiner_data->parent_irq = irq;
>  
>  	/* Disable all interrupts */
> -	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
> +	writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
>  }
>  
>  static int combiner_irq_domain_xlate(struct irq_domain *d,
> @@ -218,7 +218,7 @@ static int combiner_suspend(void)
>  
>  	for (i = 0; i < max_nr; i++)
>  		combiner_data[i].pm_save =
> -			__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
> +			readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
>  
>  	return 0;
>  }
> @@ -235,10 +235,10 @@ static void combiner_resume(void)
>  	int i;
>  
>  	for (i = 0; i < max_nr; i++) {
> -		__raw_writel(combiner_data[i].irq_mask,
> -			     combiner_data[i].base + COMBINER_ENABLE_CLEAR);
> -		__raw_writel(combiner_data[i].pm_save,
> -			     combiner_data[i].base + COMBINER_ENABLE_SET);
> +		writel_relaxed(combiner_data[i].irq_mask,
> +			       combiner_data[i].base + COMBINER_ENABLE_CLEAR);
> +		writel_relaxed(combiner_data[i].pm_save,
> +			       combiner_data[i].base + COMBINER_ENABLE_SET);
>  	}
>  }
>  
> -- 
> 2.8.3
> 

Re: [PATCH v2 1/3] irqchip: exynos_combiner: fixup reg access on be

[Matthew Leach]

Jason Cooper <jason@lakedaemon.net> writes:

> Matt, Ben,

Hi Jason,

> Both of you submitted similar patches for the same driver, same
> purpose.  Since Ben's hit my inbox first, I'll take his.

Apologies.  I missed Ben sending in that patch.

Thanks,
-- 
Matt