From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752196AbcFWTc2 (ORCPT ); Thu, 23 Jun 2016 15:32:28 -0400 Received: from megous.com ([83.167.254.221]:35706 "EHLO xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751564AbcFWTcY (ORCPT ); Thu, 23 Jun 2016 15:32:24 -0400 From: megous@megous.com To: dev@linux-sunxi.org Cc: linux-arm-kernel@lists.infradead.org, Ondrej Jirman , Rob Herring , Mark Rutland , Russell King , Maxime Ripard , Chen-Yu Tsai , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 08/14] ARM: dts: sun8i: Add r_twi I2C controller Date: Thu, 23 Jun 2016 21:20:58 +0200 Message-Id: <20160623192104.18720-9-megous@megous.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160623192104.18720-1-megous@megous.com> References: <20160623192104.18720-1-megous@megous.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ondrej Jirman H3 SoC contains I2C controller optionally available on the PL0 and PL1 pins. This patch makes this controller available. Signed-off-by: Ondrej Jirman --- arch/arm/boot/dts/sun8i-h3.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 82faefc..8d86f57 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -320,8 +320,9 @@ reg = <0x01f01428 0x4>; #clock-cells = <1>; clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; + clock-indices = <0>, <1>, <6>; + clock-output-names = "apb0_pio", "apb0_ir", "apb0_i2c"; + }; ir_clk: ir_clk@01f01454 { @@ -666,6 +667,20 @@ status = "disabled"; }; + r_twi: i2c@01f02400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_twi_pins_a>; + clocks = <&apb0_gates 6>; + clock-frequency = <100000>; + resets = <&apb0_reset 6>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, @@ -717,6 +732,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + r_twi_pins_a: r_twi@0 { + allwinner,pins = "PL0", "PL1"; + allwinner,function = "s_twi"; + allwinner,drive = ; + allwinner,pull = ; + }; }; }; }; -- 2.9.0