From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752746AbcF0TX1 (ORCPT ); Mon, 27 Jun 2016 15:23:27 -0400 Received: from down.free-electrons.com ([37.187.137.238]:58753 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751891AbcF0TXY (ORCPT ); Mon, 27 Jun 2016 15:23:24 -0400 Date: Mon, 27 Jun 2016 21:23:21 +0200 From: Maxime Ripard To: Chen-Yu Tsai Cc: Mark Brown , Lee Jones , Alessandro Zummo , Alexandre Belloni , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Michael Turquette , Stephen Boyd , rtc-linux@googlegroups.com, linux-kernel , devicetree , linux-arm-kernel , linux-clk Subject: Re: [PATCH v3 5/8] rtc: ac100: Add clk output support Message-ID: <20160627192321.GX4000@lukather> References: <1466391138-12862-1-git-send-email-wens@csie.org> <1466391138-12862-6-git-send-email-wens@csie.org> <20160622100206.GV26668@lukather> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="o/BvujNCPFVhiGON" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --o/BvujNCPFVhiGON Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jun 22, 2016 at 06:11:55PM +0800, Chen-Yu Tsai wrote: > On Wed, Jun 22, 2016 at 6:02 PM, Maxime Ripard > wrote: > > Hi, > > > > On Mon, Jun 20, 2016 at 10:52:15AM +0800, Chen-Yu Tsai wrote: > >> + /* > >> + * The ADDA 4 MHz clock is from the codec side of the AC100, > >> + * which is likely a different power domain. However, boards > >> + * always have both sides powered on, so it is impossible to > >> + * test this. > >> + */ > > > > If that ADDA clock is exposed by the codec, why are you putting it in > > the RTC? >=20 > The thing is it's not entirely clear that it's from the codec side. > I'm just inferring this from the name. (I'll make the comment clearer.) > The codec parts of the datasheet don't mention this clock at all. >=20 > Allwinner's SDK puts all the clocks under the RTC module. And the > are always on, so I can't really turn off the codec and see what > happens. That and I don't have an oscilloscope or logic analyzer. Why not just create a separate clock driver then? Thanks, Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --o/BvujNCPFVhiGON Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXcX0pAAoJEBx+YmzsjxAgH5oP/1SDE/ZGU8JvaVyGamQnRemk hGoiDYWZ5t0/fradi68lkp9imwYvPCxd8EfG6vyVw+J4/4QBXdKijPc4s5XzRuNU CaS46PpfxpPkk4UHSEjxCoXY6RHZCsexl7AIdZWXuUxinyLqqEjI3vV/rZvtdh3L 68tJsyfuamITQAkcAKp+z6g4BY3pTA8sZHJPt1NsmApHD2d5Px6qIlsRSnPNVXNa h6yvocYDeZbDqcKrWax77ZN+FROvdNdA9PcJgAJDgi1WCsirlKBZ6CxueR8ME2rd JxfGUJecdpijXhNdA39mkvMnAJ3OPBrsupLeox2pd3zN+v9IPvd4Qz3Rwp1PYk91 jvq9jmxaU5IvidDA7Mf1aV0k464S33J1oTWGMwsg2+qaciRg0RhH3Gd4KDGdEL7x 7TU2ftZE3ni+sUHBVHUgvJB07QNhZsVYmLb/7uZo5JmhGwKMcMKZTJ5wIdUbAodz kMhD8KwJ22W7camroq2odh8DQouAOki3uS4IkAMbSx/ztr8gkUnVhHl6YbjsvCqM V7dVQSTYbV3RN+CtOxyKbaRWbDLXx6AiC4tJCpr3cRbZ6XvCG5A+nC7yNQf0w/i/ XYk54xexFTZO54b0wUqSkpw/cgfj5LDkxcstTYMDRPj/B1kVUnoqAHuAWtUvzvhh FvvgltlJclLztLZyRr9T =Vh/U -----END PGP SIGNATURE----- --o/BvujNCPFVhiGON--