From: Peter Zijlstra <peterz@infradead.org>
To: xinhui <xinhui.pan@linux.vnet.ibm.com>
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
mingo@redhat.com, arnd@arndb.de, Waiman.Long@hpe.com
Subject: Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian
Date: Thu, 14 Jul 2016 11:37:33 +0200 [thread overview]
Message-ID: <20160714093733.GF30909@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <578742EA.7060108@linux.vnet.ibm.com>
On Thu, Jul 14, 2016 at 03:44:42PM +0800, xinhui wrote:
> >OK, so I poked at this a bit and I ended up with the below; but now
> >qrwlock and qspinlock are inconsistent; although I suspect qspinlock is
> >similarly busted wrt endian muck.
> >
> >Not sure what to do..
> >
> Lets talk about the qspinlock.
>
> for x86, We has already assumed that ->locked sit at the low 8 bits, as is
> smp_store_release((u8 *)lock, 0);
Right, true on x86 though :-) I noticed your PPC patches have a +3 in
there conditional on __BIG_ENDIAN.
> Then we can do a favor, export ->locked but other fields as reserved.
> say
>
> struct __qspinlock_unlcok_interface {/* what name is better?*/
> #ifdef __LITTLE_ENDIAN
> u8 locked;
> u8 reserved[3]; /* do not touch it, internally use only */
> #else
> u8 reserved[3];
> u8 locked;
> #endif
> };
Right, maybe, although something like:
static inline u8 *__qspinlock_lock_byte(struct qspinlock *lock)
{
return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
}
static inline u8 *__qrwlock_write_byte(struct qrwlock *lock)
{
return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
}
is shorter?
> > /*
> >+ * Writer states & reader shift and bias.
> >+ *
> >+ * | +0 | +1 | +2 | +3 |
> >+ * ----+----+----+----+----+
> >+ * LE | 12 | 34 | 56 | 78 | 0x12345678
> >+ * ----+----+----+----+----+
> >+ * BE | 78 | 56 | 34 | 12 | 0x12345678
> >+ * ----+----+----+----+----+
> >+ * | wr | rd |
> >+ * +----+----+----+----+
> >+ *
> > */
>
> very clearly. :)
I did one for the qspinlock code too..
diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
index b2caec7315af..9191dc454e96 100644
--- a/kernel/locking/qspinlock.c
+++ b/kernel/locking/qspinlock.c
@@ -120,6 +120,23 @@ static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
*
* This internal structure is also used by the set_locked function which
* is not restricted to _Q_PENDING_BITS == 8.
+ *
+ * | +0 | +1 | +2 | +3 |
+ * ----+----+----+----+----+
+ * LE | 78 | 56 | 34 | 12 | val = 0x12345678
+ * ----+----+----+----+----+
+ * LE | 34 | 12 | locked_pending = 0x1234
+ * ----+----+----+----+----+
+ * | L | P | tail |
+ * +----+----+----+----+
+ *
+ * ----+----+----+----+----+
+ * BE | 12 | 34 | 56 | 78 | val = 0x12345678
+ * ----+----+----+----+----+
+ * BE | 12 | 34 | locked_pending = 0x1234
+ * ----+----+----+----+----+
+ * | tail | P | L |
+ * +----+----+----+----+
*/
struct __qspinlock {
union {
next prev parent reply other threads:[~2016-07-14 9:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-20 6:20 [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian Pan Xinhui
2016-07-13 19:54 ` Peter Zijlstra
2016-07-13 20:40 ` Peter Zijlstra
2016-07-14 1:54 ` Waiman Long
2016-07-14 7:44 ` xinhui
2016-07-14 9:37 ` Peter Zijlstra [this message]
2016-07-14 9:46 ` Peter Zijlstra
2016-07-15 0:41 ` Boqun Feng
2016-07-15 6:28 ` panxinhui
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