From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754833AbcGTTDI (ORCPT ); Wed, 20 Jul 2016 15:03:08 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:36700 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751721AbcGTTDF (ORCPT ); Wed, 20 Jul 2016 15:03:05 -0400 Date: Wed, 20 Jul 2016 14:03:03 -0500 From: Rob Herring To: Andrey Pronin Cc: Jarkko Sakkinen , Peter Huewe , Marcel Selhorst , Jason Gunthorpe , tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, Christophe Ricard , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/2] tpm: devicetree: document properties for cr50 Message-ID: <20160720190303.GA5620@rob-hp-laptop> References: <1468549218-19215-1-git-send-email-apronin@chromium.org> <5274cc806888a709c639e701dad894543885b2c9.1468985673.git.apronin@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5274cc806888a709c639e701dad894543885b2c9.1468985673.git.apronin@chromium.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 19, 2016 at 08:41:24PM -0700, Andrey Pronin wrote: > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 > firmware. Several timing-related properties that may differ from > one firmware version to another are added to devicetree. > Document these properties. > > Signed-off-by: Andrey Pronin > --- > .../devicetree/bindings/security/tpm/cr50_spi.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt > > diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt > new file mode 100644 > index 0000000..f212b6b > --- /dev/null > +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt > @@ -0,0 +1,32 @@ > +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. > + > +H1 Secure Microcontroller running Cr50 firmware provides several > +functions, including TPM-like functionality. It communicates over > +SPI using the FIFO protocol described in the PTP Spec, section 6. > + > +Required properties: > +- compatible: Should be "google,cr50". > +- spi-max-frequency: Maximum SPI frequency. > + > +Optional properties: > +- access-delay-ms: Required delay between subsequent transactions on SPI. As I mentioned, there may be common properties. It doesn't seem you looked, so I did: - spi-rx-delay-us - (optional) Microsecond delay after a read transfer. - spi-tx-delay-us - (optional) Microsecond delay after a write transfer. Seems to me setting one or both of these should work for you. > +- sleep-delay-ms: Time after the last SPI activity, after which the chip > + may go to sleep. > +- wake-start-delay-ms: Time after initiating wake up before the chip is > + ready to accept commands over SPI. I also asked why these 2 can't be hard-coded in the driver? > + > +Example: > + > +&spi0 { > + status = "okay"; > + > + cr50@0 { > + compatible = "google,cr50"; > + reg = <0>; > + spi-max-frequency = <800000>; > + > + access-delay-ms = <2>; > + sleep-delay-ms = <1000>; > + wake-start-delay-ms = <60>; > + }; > +}; > -- > 2.6.6 >