From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752201AbcG2JjN (ORCPT ); Fri, 29 Jul 2016 05:39:13 -0400 Received: from mga01.intel.com ([192.55.52.88]:49068 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750752AbcG2JjK (ORCPT ); Fri, 29 Jul 2016 05:39:10 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,438,1464678000"; d="scan'208";a="1026155738" Date: Fri, 29 Jul 2016 12:39:05 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Matt Roper Cc: Lyude , intel-gfx@lists.freedesktop.org, Maarten Lankhorst , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Daniel Vetter Subject: Re: [Intel-gfx] [PATCH v4 0/6] Finally fix watermarks Message-ID: <20160729093905.GU4329@intel.com> References: <1469554483-24999-1-git-send-email-cpaul@redhat.com> <20160729000352.GR32025@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20160729000352.GR32025@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 28, 2016 at 05:03:52PM -0700, Matt Roper wrote: > This is completely untested (and probably horribly broken/buggy), but > here's a quick mockup of the general approach I was thinking for > ensuring DDB & WM's can be updated together while ensuring the > three-step pipe flushing process is honored: > > https://github.com/mattrope/kernel/commits/experimental/lyude_ddb > > Basically the idea is to take note of what's happening to the pipe's DDB > allocation (shrinking, growing, unchanged, etc.) during the atomic check > phase; Didn't look too closely, but I think you can't actually do that unless you lock all the crtcs whenever the number of active pipes is goind to change. Meaning we'd essentially be back to the one-big-modeset-lock apporach, which will cause missed flips and whanot on the other pipes. The alternative I think would consist of: - make sure level 0 watermark never exceeds total_ddb_size/max_pipes, so that a modeset doesn't have to care about the wms for the other pipes not fitting in - level 1+ watermarks would be checked against total_ddb_size - protect the plane/pipe commit with the wm mutex whenever the wms need to be reprogrammed - keep the flush_wm thing around for the case when ddb size does get changed, protect it with the wm lock - when programming wms, we will first filter out any level that doesn't fit in with the current ddb size, and then program the rest in - potentially introduce per-pipe wm locks if the one big lock looks like an issue, which it might if the flush_wm holds it all the way through > then during the commit phase, we loop over the CRTC's three times > instead of just once, but only operate on a subset of the CRTC's in each > loop. While operating on each CRTC, the plane, WM, and DDB all get > programmed together and have a single flush for all three. > > > > > Matt > > On Tue, Jul 26, 2016 at 01:34:36PM -0400, Lyude wrote: > > Latest version of https://lkml.org/lkml/2016/7/26/290 . Resending the whole > > thing to keep it in one place. > > > > Lyude (5): > > drm/i915/skl: Add support for the SAGV, fix underrun hangs > > drm/i915/skl: Only flush pipes when we change the ddb allocation > > drm/i915/skl: Fix extra whitespace in skl_flush_wm_values() > > drm/i915/skl: Update plane watermarks atomically during plane updates > > drm/i915/skl: Always wait for pipes to update after a flush > > > > Matt Roper (1): > > drm/i915/gen9: Only copy WM results for changed pipes to skl_hw > > > > drivers/gpu/drm/i915/i915_drv.h | 3 + > > drivers/gpu/drm/i915/i915_reg.h | 5 + > > drivers/gpu/drm/i915/intel_display.c | 24 ++++ > > drivers/gpu/drm/i915/intel_drv.h | 4 + > > drivers/gpu/drm/i915/intel_pm.c | 240 +++++++++++++++++++++++++++++++---- > > drivers/gpu/drm/i915/intel_sprite.c | 2 + > > 6 files changed, 255 insertions(+), 23 deletions(-) > > > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 -- Ville Syrjälä Intel OTC