From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934090AbcHYNd6 (ORCPT ); Thu, 25 Aug 2016 09:33:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38392 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934000AbcHYNd4 (ORCPT ); Thu, 25 Aug 2016 09:33:56 -0400 Date: Thu, 25 Aug 2016 15:33:25 +0200 From: Oleg Nesterov To: Will Deacon Cc: Pratyush Anand , linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, wcohen@redhat.com, dave.long@linaro.org, steve.capper@linaro.org, srikar@linux.vnet.ibm.com, vijaya.kumar@caviumnetworks.com, Shi Yang , Andre Przywara , Ard Biesheuvel , Ashok Kumar , James Morse , Jungseok Lee , "Kirill A. Shutemov" , Mark Rutland , Masami Hiramatsu , Robin Murphy , Sandeepa Prabhu , Shaokun Zhang , "Suzuki K. Poulose" , Vladimir Murzin Subject: Re: [PATCH 5/5] arm64: Add uprobe support Message-ID: <20160825133325.GA7653@redhat.com> References: <20160809184943.GA17112@redhat.com> <20160824071308.GA24311@localhost.localdomain> <20160824154711.GA25531@redhat.com> <20160824155649.GG16944@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160824155649.GG16944@arm.com> User-Agent: Mutt/1.5.18 (2008-05-17) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Thu, 25 Aug 2016 13:33:56 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/24, Will Deacon wrote: > > On Wed, Aug 24, 2016 at 05:47:11PM +0200, Oleg Nesterov wrote: > > On 08/24, Pratyush Anand wrote: > > > > > > > I don't think we want user_{enable,disable{_single_step in the long term, > > > > please look at 9bd1190a11c9d2 "uprobes/x86: Do not (ab)use TIF_SINGLESTEP > > > > /user_*_single_step() for single-stepping". it seems that ARM64 sets/clears > > > > TIF_SINGLESTEP. You can also lool at saved_tf logic, probably ARM64 needs > > > > the same. > > > > > > IIUC, then you mean that TIF_SINGLESTEP is a per task flag, > > > > Yes, and nobody but ptrace should use it, otherwise ptrace/uprobes can confuse > > each other. And uprobes simply doesn't need to set/clear it. > > We're already using it for kprobes, hw_breakpoint and kgdb as well as > ptrace, so I'd rather uprobes either followed existing practice, or we > converted everybody off the current code. And perhaps this is fine for arm64, I do not know. > In what way do things get confused? Say, arch_uprobe_post_xol() should not blindly do user_disable_single_step(), this can confuse ptrace if TIF_SINGLESTEP was set by debugger which wants to step over the probed insn. > > I can't really answer since I know nothing about arm. x86 just needs to set > > X86_EFLAGS_TF, I guess arm needs to modify some register too? > > We have {user,kernel}_{enable,disable}_single_step for managing the various > registers controlling the single-step state machine on arm64. Yes, and perhaps uprobes can just do set_regs_spsr_ss() ? I never looked into arch/arm64/, but it seems that we only need to ensure that call_step_hook() will be called even if user_mode() == T, why do we need TIF_SINGLESTEP ? Nevermind. I can be easily wrong and let me repeat that I agree with user_{enable,disable}_single_step in the initial version in any case. Oleg.