From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755669AbcH3Pic (ORCPT ); Tue, 30 Aug 2016 11:38:32 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:35589 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751527AbcH3Pi2 (ORCPT ); Tue, 30 Aug 2016 11:38:28 -0400 From: Iaroslav Gridin To: andy.gross@linaro.org Cc: david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Voker57 Subject: [PATCH] ARM: dts: msm8974: Add definitions for QCE & cryptobam Date: Tue, 30 Aug 2016 18:37:40 +0300 Message-Id: <20160830153740.13275-1-voker57@gmail.com> X-Mailer: git-send-email 2.9.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Voker57 Add device tree definitions for Qualcomm Cryptography engine and its BAM Signed-off-by: Iaroslav Gridin --- arch/arm/boot/dts/qcom-msm8974.dtsi | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 561d4d1..c0da739 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -287,6 +287,48 @@ reg = <0xf9011000 0x1000>; }; + cryptobam: dma@fd444000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfd444000 0x15000>; + interrupts = <0 236 0>; + clocks = <&gcc GCC_CE2_AHB_CLK>, + <&gcc GCC_CE2_AXI_CLK>, + <&gcc GCC_CE2_CLK>; + clock-names = "bam_clk", "axi_clk", "core_clk"; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + }; + + qcom,qcrypto@fd440000 { + compatible = "qcom,crypto-v5.1"; + reg = <0xfd45a000 0x6000>; + reg-names = "crypto-base"; + interrupts = <0 236 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <1>; + qcom,ce-device = <0>; + clocks = <&gcc GCC_CE2_CLK>, + <&gcc GCC_CE2_AHB_CLK>, + <&gcc GCC_CE2_AXI_CLK>, + <&gcc CE2_CLK_SRC>; + + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + clock-names = "core", "iface", "bus", "core_src"; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-ahash-algo; + qcom,msm-bus,vectors-KBps = <56 512 0 0>, + <56 512 3936000 393600>; + }; + + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; -- 2.9.3