From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: ngo Molnar <mingo@redhat.com>,
linux-kernel@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: [PATCH v1 1/2] x86/platform/intel-mid: Add Intel Penwell to ID table
Date: Thu, 8 Sep 2016 13:32:31 +0300 [thread overview]
Message-ID: <20160908103232.137587-1-andriy.shevchenko@linux.intel.com> (raw)
The commit ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support
Penwell") enables the PWRMU driver on platforms based on Intel Penwell,
unfortunately this is not enough.
Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the
future add a comment to both drivers.
Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/platform/intel-mid/pwr.c | 1 +
drivers/pci/pci-mid.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 2dfe998..146ed54 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = {
.set_initial_state = mid_set_initial_state,
};
+/* This table should be in sync with the one in drivers/pci/pci-mid.c */
static const struct pci_device_id mid_pwr_pci_ids[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c
index b7ea64f..55f453d 100644
--- a/drivers/pci/pci-mid.c
+++ b/drivers/pci/pci-mid.c
@@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = {
#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
+/*
+ * This table should be in sync with the one in
+ * arch/x86/platform/intel-mid/pwr.c.
+ */
static const struct x86_cpu_id lpss_cpu_ids[] = {
+ ICPU(INTEL_FAM6_ATOM_PENWELL),
ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
{}
};
--
2.9.3
next reply other threads:[~2016-09-08 10:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-08 10:32 Andy Shevchenko [this message]
2016-09-08 10:32 ` [PATCH v1 2/2] x86/platform/intel-mid: Keep SRAM powered on at boot Andy Shevchenko
2016-09-08 13:19 ` [tip:x86/platform] " tip-bot for Andy Shevchenko
2016-09-08 13:19 ` [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID table tip-bot for Andy Shevchenko
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