* [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC
@ 2016-09-12 9:01 Jiancheng Xue
2016-09-12 13:55 ` kbuild test robot
2016-09-14 21:01 ` Stephen Boyd
0 siblings, 2 replies; 5+ messages in thread
From: Jiancheng Xue @ 2016-09-12 9:01 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland
Cc: linux-clk, devicetree, linux-kernel, yanhaifeng, gaofei,
hermit.wangheming, scott.bambrough, mark.gregotski
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
.../devicetree/bindings/clock/hi3519-crg.txt | 46 ----
.../devicetree/bindings/clock/hisi-crg.txt | 49 ++++
drivers/clk/hisilicon/Kconfig | 8 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/crg-hi3798cv200.c | 304 +++++++++++++++++++++
drivers/clk/hisilicon/crg.h | 39 +++
include/dt-bindings/clock/histb-clock.h | 64 +++++
7 files changed, 465 insertions(+), 46 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt
create mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
create mode 100644 drivers/clk/hisilicon/crg.h
create mode 100644 include/dt-bindings/clock/histb-clock.h
diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
deleted file mode 100644
index acd1f23..0000000
--- a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Hisilicon Hi3519 Clock and Reset Generator(CRG)
-
-The Hi3519 CRG module provides clock and reset signals to various
-controllers within the SoC.
-
-This binding uses the following bindings:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/reset/reset.txt
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes use this identifier
-to specify the clock which they consume.
-
-All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
-
-- #reset-cells: should be 2.
-
-A reset signal can be controlled by writing a bit register in the CRG module.
-The reset specifier consists of two cells. The first cell represents the
-register offset relative to the base address. The second cell represents the
-bit index in the register.
-
-Example: CRG nodes
-CRG: clock-reset-controller@12010000 {
- compatible = "hisilicon,hi3519-crg";
- reg = <0x12010000 0x10000>;
- #clock-cells = <1>;
- #reset-cells = <2>;
-};
-
-Example: consumer nodes
-i2c0: i2c@12110000 {
- compatible = "hisilicon,hi3519-i2c";
- reg = <0x12110000 0x1000>;
- clocks = <&CRG HI3519_I2C0_RST>;
- resets = <&CRG 0xe4 0>;
-};
diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt
new file mode 100644
index 0000000..e3919b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt
@@ -0,0 +1,49 @@
+* HiSilicon Clock and Reset Generator(CRG)
+
+The CRG module provides clock and reset signals to various
+modules within the SoC.
+
+This binding uses the following bindings:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "hisilicon,hi3516cv300-crg"
+ - "hisilicon,hi3519-crg"
+ - "hisilicon,hi3798cv200-crg"
+ - "hisilicon,hi3798cv200-sysctrl"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller@12010000 {
+ compatible = "hisilicon,hi3519-crg";
+ reg = <0x12010000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@12110000 {
+ compatible = "hisilicon,hi3519-i2c";
+ reg = <0x12110000 0x1000>;
+ clocks = <&CRG HI3519_I2C0_RST>;
+ resets = <&CRG 0xe4 0>;
+};
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 3f537a0..c41b6d2 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -6,6 +6,14 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3798CV200
+ tristate "Hi3798CV200 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ select RESET_HISI
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3798cv200.
+
config COMMON_CLK_HI6220
bool "Hi6220 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index e169ec7..233d809 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
+obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
new file mode 100644
index 0000000..b763b99
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -0,0 +1,304 @@
+/*
+ * Hi3798CV200 Clock and Reset Generator Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/histb-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include "clk.h"
+#include "crg.h"
+#include "reset.h"
+
+/* hi3798CV200 core CRG */
+#define INNER_CLK_OFFSET 64
+#define FIXED_24M 65
+#define FIXED_25M 66
+#define FIXED_50M 67
+#define FIXED_75M 68
+#define FIXED_100M 69
+#define FIXED_150M 70
+#define FIXED_200M 71
+#define FIXED_250M 72
+#define FIXED_300M 73
+#define FIXED_400M 74
+#define MMC_MUX 75
+
+#define HI3798CV200_CRG_NR_CLKS 128
+
+static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
+ { OSC_CLK, "clk_osc", NULL, 0, 24000000, },
+ { APB_CLK, "clk_apb", NULL, 0, 100000000, },
+ { AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
+ { FIXED_24M, "24m", NULL, 0, 24000000, },
+ { FIXED_25M, "25m", NULL, 0, 25000000, },
+ { FIXED_50M, "50m", NULL, 0, 50000000, },
+ { FIXED_75M, "75m", NULL, 0, 75000000, },
+ { FIXED_100M, "100m", NULL, 0, 100000000, },
+ { FIXED_150M, "150m", NULL, 0, 150000000, },
+ { FIXED_200M, "200m", NULL, 0, 200000000, },
+ { FIXED_250M, "250m", NULL, 0, 250000000, },
+};
+
+static const char *const mmc_mux_p[] = {
+ "100m", "50m", "25m", "200m", "150m" };
+static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
+
+static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
+ { MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
+ /* UART */
+ { UART2_CLK, "clk_uart2", "75m",
+ CLK_SET_RATE_PARENT, 0x68, 4, 0, },
+ /* I2C */
+ { I2C0_CLK, "clk_i2c0", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
+ { I2C1_CLK, "clk_i2c1", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
+ { I2C2_CLK, "clk_i2c2", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
+ { I2C3_CLK, "clk_i2c3", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
+ { I2C4_CLK, "clk_i2c4", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
+ /* SPI */
+ { SPI0_CLK, "clk_spi0", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x70, 0, 0, },
+ /* SDIO */
+ { SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
+ CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
+ { SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux",
+ CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
+ /* EMMC */
+ { MMC_BIU_CLK, "clk_mmc_biu", "200m",
+ CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
+ { MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
+ CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
+ /* PCIE*/
+ { PCIE_BUS_CLK, "clk_pcie_bus", "200m",
+ CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
+ { PCIE_SYS_CLK, "clk_pcie_sys", "100m",
+ CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
+ { PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
+ CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
+ { PCIE_AUX_CLK, "clk_pcie_aux", "24m",
+ CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
+};
+
+static struct hisi_clock_data *hi3798cv200_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
+ ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
+ ARRAY_SIZE(hi3798cv200_mux_clks),
+ clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
+ ARRAY_SIZE(hi3798cv200_gate_clks),
+ clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
+ ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ clk_data);
+
+unregister_mux:
+ hisi_clk_unregister_mux(hi3798cv200_mux_clks,
+ ARRAY_SIZE(hi3798cv200_mux_clks),
+ clk_data);
+unregister_gate:
+ hisi_clk_unregister_gate(hi3798cv200_gate_clks,
+ ARRAY_SIZE(hi3798cv200_gate_clks),
+ clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3798cv200_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3798cv200_gate_clks,
+ ARRAY_SIZE(hi3798cv200_gate_clks),
+ crg->clk_data);
+ hisi_clk_unregister_mux(hi3798cv200_mux_clks,
+ ARRAY_SIZE(hi3798cv200_mux_clks),
+ crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
+ ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ crg->clk_data);
+}
+
+static struct hisi_crg_funcs hi3798cv200_crg_funcs = {
+ .register_clks = hi3798cv200_clk_register,
+ .unregister_clks = hi3798cv200_clk_unregister,
+};
+
+/* hi3798CV200 sysctrl CRG */
+
+#define HI3798CV200_SYSCTRL_NR_CLKS 16
+
+static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
+ { IR_CLK, "clk_ir", "100m",
+ CLK_SET_RATE_PARENT, 0x48, 4, 0, },
+ { TIMER01_CLK, "clk_timer01", "24m",
+ CLK_SET_RATE_PARENT, 0x48, 6, 0, },
+ { UART0_CLK, "clk_uart0", "75m",
+ CLK_SET_RATE_PARENT, 0x48, 10, 0, },
+};
+
+static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
+ ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+ clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
+ ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+ clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
+ ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+ crg->clk_data);
+}
+
+static struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
+ .register_clks = hi3798cv200_sysctrl_clk_register,
+ .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
+};
+
+static const struct of_device_id hi3798cv200_crg_match_table[] = {
+ { .compatible = "hisilicon,hi3798cv200-crg",
+ .data = &hi3798cv200_crg_funcs},
+ { .compatible = "hisilicon,hi3798cv200-sysctrl",
+ .data = &hi3798cv200_sysctrl_funcs},
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
+
+static int hi3798cv200_crg_probe(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg;
+ const struct of_device_id *match;
+
+ crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
+ if (!crg)
+ return -ENOMEM;
+
+ match = of_match_node(hi3798cv200_crg_match_table, pdev->dev.of_node);
+ crg->funcs = (struct hisi_crg_funcs *)match->data;
+
+ crg->rstc = hisi_reset_init(pdev);
+ if (!crg->rstc)
+ return -ENOMEM;
+
+ crg->clk_data = crg->funcs->register_clks(pdev);
+ if (IS_ERR(crg->clk_data)) {
+ hisi_reset_exit(crg->rstc);
+ return PTR_ERR(crg->clk_data);
+ }
+
+ platform_set_drvdata(pdev, crg);
+ return 0;
+}
+
+static int hi3798cv200_crg_remove(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ hisi_reset_exit(crg->rstc);
+ crg->funcs->unregister_clks(pdev);
+ return 0;
+}
+
+static struct platform_driver hi3798cv200_crg_driver = {
+ .probe = hi3798cv200_crg_probe,
+ .remove = hi3798cv200_crg_remove,
+ .driver = {
+ .name = "hi3798cv200-crg",
+ .of_match_table = hi3798cv200_crg_match_table,
+ },
+};
+
+static int __init hi3798cv200_crg_init(void)
+{
+ return platform_driver_register(&hi3798cv200_crg_driver);
+}
+core_initcall(hi3798cv200_crg_init);
+
+static void __exit hi3798cv200_crg_exit(void)
+{
+ platform_driver_unregister(&hi3798cv200_crg_driver);
+}
+module_exit(hi3798cv200_crg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
new file mode 100644
index 0000000..145b929
--- /dev/null
+++ b/drivers/clk/hisilicon/crg.h
@@ -0,0 +1,39 @@
+/*
+ * HiSilicon Clock and Reset Driver Header
+ *
+ * Copyright (c) 2016 HiSilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __HISI_CRG_H
+#define __HISI_CRG_H
+
+struct hisi_clock_data;
+struct hisi_reset_controller;
+
+struct hisi_crg_funcs {
+ struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
+ void (*unregister_clks)(struct platform_device *pdev);
+};
+
+struct hisi_crg_dev {
+ struct hisi_clock_data *clk_data;
+ struct hisi_reset_controller *rstc;
+ struct hisi_crg_funcs *funcs;
+};
+
+#endif /* __HISI_CRG_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
new file mode 100644
index 0000000..7f23298
--- /dev/null
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define OSC_CLK 0
+#define APB_CLK 1
+#define AHB_CLK 2
+#define UART1_CLK 3
+#define UART2_CLK 4
+#define UART3_CLK 5
+#define I2C0_CLK 6
+#define I2C1_CLK 7
+#define I2C2_CLK 8
+#define I2C3_CLK 9
+#define I2C4_CLK 10
+#define I2C5_CLK 11
+#define SPI0_CLK 12
+#define SPI1_CLK 13
+#define SPI2_CLK 14
+#define SCI_CLK 15
+#define FMC_CLK 16
+#define MMC_BIU_CLK 17
+#define MMC_CIU_CLK 18
+#define MMC_DRV_CLK 19
+#define MMC_SAMPLE_CLK 20
+#define SDIO0_BIU_CLK 21
+#define SDIO0_CIU_CLK 22
+#define SDIO0_DRV_CLK 23
+#define SDIO0_SAMPLE_CLK 24
+#define PCIE_AUX_CLK 25
+#define PCIE_PIPE_CLK 26
+#define PCIE_SYS_CLK 27
+#define PCIE_BUS_CLK 28
+#define ETH0_MAC_CLK 29
+#define ETH0_MACIF_CLK 30
+#define ETH1_MAC_CLK 31
+#define ETH1_MACIF_CLK 32
+
+/* clocks provided by mcu CRG */
+#define MCE_CLK 1
+#define IR_CLK 2
+#define TIMER01_CLK 3
+#define LEDC_CLK 4
+#define UART0_CLK 5
+#define LSADC_CLK 6
+
+#endif /* __DTS_HISTB_CLOCK_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC
2016-09-12 9:01 [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Jiancheng Xue
@ 2016-09-12 13:55 ` kbuild test robot
2016-09-13 2:45 ` Jiancheng Xue
2016-09-14 21:01 ` Stephen Boyd
1 sibling, 1 reply; 5+ messages in thread
From: kbuild test robot @ 2016-09-12 13:55 UTC (permalink / raw)
To: Jiancheng Xue
Cc: kbuild-all, mturquette, sboyd, robh+dt, mark.rutland, linux-clk,
devicetree, linux-kernel, yanhaifeng, gaofei, hermit.wangheming,
scott.bambrough, mark.gregotski
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Hi Jiancheng,
[auto build test ERROR on clk/clk-next]
[also build test ERROR on v4.8-rc6 next-20160912]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Jiancheng-Xue/clk-hisilicon-add-CRG-driver-for-Hi3798CV200-SoC/20160912-175733
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
In file included from drivers/clk/hisilicon/crg-hi3798cv200.c:22:0:
>> drivers/clk/hisilicon/crg-hi3798cv200.c:245:25: error: 'hi3798cv200_clk_match_table' undeclared here (not in a function)
MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
^
include/linux/module.h:213:21: note: in definition of macro 'MODULE_DEVICE_TABLE'
extern const typeof(name) __mod_##type##__##name##_device_table \
^
>> include/linux/module.h:213:27: error: '__mod_of__hi3798cv200_clk_match_table_device_table' aliased to undefined symbol 'hi3798cv200_clk_match_table'
extern const typeof(name) __mod_##type##__##name##_device_table \
^
>> drivers/clk/hisilicon/crg-hi3798cv200.c:245:1: note: in expansion of macro 'MODULE_DEVICE_TABLE'
MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
^
vim +/hi3798cv200_clk_match_table +245 drivers/clk/hisilicon/crg-hi3798cv200.c
239 { .compatible = "hisilicon,hi3798cv200-crg",
240 .data = &hi3798cv200_crg_funcs},
241 { .compatible = "hisilicon,hi3798cv200-sysctrl",
242 .data = &hi3798cv200_sysctrl_funcs},
243 { }
244 };
> 245 MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
246
247 static int hi3798cv200_crg_probe(struct platform_device *pdev)
248 {
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 58527 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC
2016-09-12 13:55 ` kbuild test robot
@ 2016-09-13 2:45 ` Jiancheng Xue
0 siblings, 0 replies; 5+ messages in thread
From: Jiancheng Xue @ 2016-09-13 2:45 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland
Cc: linux-clk, devicetree, linux-kernel, yanhaifeng, gaofei,
hermit.wangheming, scott.bambrough, mark.gregotski
Hi all,
Sorry. I'll fixed this compiling error in the next version.
Regards,
Jiancheng
On 2016/9/12 21:55, kbuild test robot wrote:
> Hi Jiancheng,
>
> [auto build test ERROR on clk/clk-next]
> [also build test ERROR on v4.8-rc6 next-20160912]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
> [Check https://git-scm.com/docs/git-format-patch for more information]
>
> url: https://github.com/0day-ci/linux/commits/Jiancheng-Xue/clk-hisilicon-add-CRG-driver-for-Hi3798CV200-SoC/20160912-175733
> base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
> reproduce:
> wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm
>
> All error/warnings (new ones prefixed by >>):
>
> In file included from drivers/clk/hisilicon/crg-hi3798cv200.c:22:0:
>>> drivers/clk/hisilicon/crg-hi3798cv200.c:245:25: error: 'hi3798cv200_clk_match_table' undeclared here (not in a function)
> MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
> ^
> include/linux/module.h:213:21: note: in definition of macro 'MODULE_DEVICE_TABLE'
> extern const typeof(name) __mod_##type##__##name##_device_table \
> ^
>>> include/linux/module.h:213:27: error: '__mod_of__hi3798cv200_clk_match_table_device_table' aliased to undefined symbol 'hi3798cv200_clk_match_table'
> extern const typeof(name) __mod_##type##__##name##_device_table \
> ^
>>> drivers/clk/hisilicon/crg-hi3798cv200.c:245:1: note: in expansion of macro 'MODULE_DEVICE_TABLE'
> MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
> ^
>
> vim +/hi3798cv200_clk_match_table +245 drivers/clk/hisilicon/crg-hi3798cv200.c
>
> 239 { .compatible = "hisilicon,hi3798cv200-crg",
> 240 .data = &hi3798cv200_crg_funcs},
> 241 { .compatible = "hisilicon,hi3798cv200-sysctrl",
> 242 .data = &hi3798cv200_sysctrl_funcs},
> 243 { }
> 244 };
> > 245 MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
> 246
> 247 static int hi3798cv200_crg_probe(struct platform_device *pdev)
> 248 {
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC
2016-09-12 9:01 [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Jiancheng Xue
2016-09-12 13:55 ` kbuild test robot
@ 2016-09-14 21:01 ` Stephen Boyd
2016-09-18 1:49 ` Jiancheng Xue
1 sibling, 1 reply; 5+ messages in thread
From: Stephen Boyd @ 2016-09-14 21:01 UTC (permalink / raw)
To: Jiancheng Xue
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, yanhaifeng, gaofei, hermit.wangheming,
scott.bambrough, mark.gregotski
On 09/12, Jiancheng Xue wrote:
> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
> Generator) module generates clock and reset signals used
> by other module blocks on SoC.
>
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Overall looks fine. Just a few nitpicks.
> ---
> .../devicetree/bindings/clock/hi3519-crg.txt | 46 ----
> .../devicetree/bindings/clock/hisi-crg.txt | 49 ++++
I wonder if git format-patch -M would make it more apparent about
what's changed across the file rename?
> drivers/clk/hisilicon/Kconfig | 8 +
> drivers/clk/hisilicon/Makefile | 1 +
> drivers/clk/hisilicon/crg-hi3798cv200.c | 304 +++++++++++++++++++++
> drivers/clk/hisilicon/crg.h | 39 +++
> include/dt-bindings/clock/histb-clock.h | 64 +++++
> 7 files changed, 465 insertions(+), 46 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
> create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt
> create mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
> create mode 100644 drivers/clk/hisilicon/crg.h
> create mode 100644 include/dt-bindings/clock/histb-clock.h
>
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index e169ec7..233d809 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
> +obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
Tab this out?
> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
> obj-$(CONFIG_RESET_HISI) += reset.o
> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
> diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
> new file mode 100644
> index 0000000..b763b99
> --- /dev/null
> +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
> @@ -0,0 +1,304 @@
[...]
> +
> +static struct hisi_crg_funcs hi3798cv200_crg_funcs = {
const?
> + .register_clks = hi3798cv200_clk_register,
> + .unregister_clks = hi3798cv200_clk_unregister,
> +};
> +
> +/* hi3798CV200 sysctrl CRG */
> +
> +#define HI3798CV200_SYSCTRL_NR_CLKS 16
> +
> +static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
> + { IR_CLK, "clk_ir", "100m",
> + CLK_SET_RATE_PARENT, 0x48, 4, 0, },
> + { TIMER01_CLK, "clk_timer01", "24m",
> + CLK_SET_RATE_PARENT, 0x48, 6, 0, },
> + { UART0_CLK, "clk_uart0", "75m",
> + CLK_SET_RATE_PARENT, 0x48, 10, 0, },
> +};
> +
> +static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
> + struct platform_device *pdev)
> +{
> + struct hisi_clock_data *clk_data;
> + int ret;
> +
> + clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
> + if (!clk_data)
> + return ERR_PTR(-ENOMEM);
> +
> + ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
> + ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
> + clk_data);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + ret = of_clk_add_provider(pdev->dev.of_node,
> + of_clk_src_onecell_get, &clk_data->clk_data);
> + if (ret)
> + goto unregister_gate;
> +
> + return clk_data;
> +
> +unregister_gate:
> + hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
> + ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
> + clk_data);
> + return ERR_PTR(ret);
> +}
> +
> +static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
> +{
> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
> +
> + of_clk_del_provider(pdev->dev.of_node);
> +
> + hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
> + ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
> + crg->clk_data);
> +}
> +
> +static struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
const?
> + .register_clks = hi3798cv200_sysctrl_clk_register,
> + .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
> +};
> +
> +static const struct of_device_id hi3798cv200_crg_match_table[] = {
> + { .compatible = "hisilicon,hi3798cv200-crg",
> + .data = &hi3798cv200_crg_funcs},
Nitpick: please add a space before }
> + { .compatible = "hisilicon,hi3798cv200-sysctrl",
> + .data = &hi3798cv200_sysctrl_funcs},
Nitpick: please add a space before }
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
> +
> +static int hi3798cv200_crg_probe(struct platform_device *pdev)
> +{
> + struct hisi_crg_dev *crg;
> + const struct of_device_id *match;
> +
> + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
> + if (!crg)
> + return -ENOMEM;
> +
> + match = of_match_node(hi3798cv200_crg_match_table, pdev->dev.of_node);
> + crg->funcs = (struct hisi_crg_funcs *)match->data;
We can use of_device_get_match_data() here to simplify things.
> +
> + crg->rstc = hisi_reset_init(pdev);
> + if (!crg->rstc)
> + return -ENOMEM;
> +
> diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
> new file mode 100644
> index 0000000..145b929
> --- /dev/null
> +++ b/drivers/clk/hisilicon/crg.h
> @@ -0,0 +1,39 @@
> +/*
> + * HiSilicon Clock and Reset Driver Header
> + *
> + * Copyright (c) 2016 HiSilicon Limited.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *
> + */
> +
> +#ifndef __HISI_CRG_H
> +#define __HISI_CRG_H
Weird tab here. Please replace with space.
> +
> +struct hisi_clock_data;
> +struct hisi_reset_controller;
> +
> +struct hisi_crg_funcs {
> + struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
> + void (*unregister_clks)(struct platform_device *pdev);
> +};
> +
> +struct hisi_crg_dev {
> + struct hisi_clock_data *clk_data;
> + struct hisi_reset_controller *rstc;
> + struct hisi_crg_funcs *funcs;
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC
2016-09-14 21:01 ` Stephen Boyd
@ 2016-09-18 1:49 ` Jiancheng Xue
0 siblings, 0 replies; 5+ messages in thread
From: Jiancheng Xue @ 2016-09-18 1:49 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, yanhaifeng, gaofei, hermit.wangheming,
scott.bambrough, mark.gregotski
On 2016/9/15 5:01, Stephen Boyd wrote:
> On 09/12, Jiancheng Xue wrote:
>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
>> Generator) module generates clock and reset signals used
>> by other module blocks on SoC.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
>
> Overall looks fine. Just a few nitpicks.
>
Hi Stephen,
Thanks for all your comments. I'll refine this patch
according to your suggestions and send a new version.
Best Regards,
Jiancheng
>> ---
>> .../devicetree/bindings/clock/hi3519-crg.txt | 46 ----
>> .../devicetree/bindings/clock/hisi-crg.txt | 49 ++++
>
> I wonder if git format-patch -M would make it more apparent about
> what's changed across the file rename?
>
>> drivers/clk/hisilicon/Kconfig | 8 +
>> drivers/clk/hisilicon/Makefile | 1 +
>> drivers/clk/hisilicon/crg-hi3798cv200.c | 304 +++++++++++++++++++++
>> drivers/clk/hisilicon/crg.h | 39 +++
>> include/dt-bindings/clock/histb-clock.h | 64 +++++
>> 7 files changed, 465 insertions(+), 46 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt
>> create mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
>> create mode 100644 drivers/clk/hisilicon/crg.h
>> create mode 100644 include/dt-bindings/clock/histb-clock.h
>>
>> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
>> index e169ec7..233d809 100644
>> --- a/drivers/clk/hisilicon/Makefile
>> +++ b/drivers/clk/hisilicon/Makefile
>> @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
>> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
>> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
>> obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
>> +obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
>
> Tab this out?
>
>> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
>> obj-$(CONFIG_RESET_HISI) += reset.o
>> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
>> diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
>> new file mode 100644
>> index 0000000..b763b99
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
>> @@ -0,0 +1,304 @@
> [...]
>> +
>> +static struct hisi_crg_funcs hi3798cv200_crg_funcs = {
>
> const?
>
>> + .register_clks = hi3798cv200_clk_register,
>> + .unregister_clks = hi3798cv200_clk_unregister,
>> +};
>> +
>> +/* hi3798CV200 sysctrl CRG */
>> +
>> +#define HI3798CV200_SYSCTRL_NR_CLKS 16
>> +
>> +static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
>> + { IR_CLK, "clk_ir", "100m",
>> + CLK_SET_RATE_PARENT, 0x48, 4, 0, },
>> + { TIMER01_CLK, "clk_timer01", "24m",
>> + CLK_SET_RATE_PARENT, 0x48, 6, 0, },
>> + { UART0_CLK, "clk_uart0", "75m",
>> + CLK_SET_RATE_PARENT, 0x48, 10, 0, },
>> +};
>> +
>> +static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
>> + struct platform_device *pdev)
>> +{
>> + struct hisi_clock_data *clk_data;
>> + int ret;
>> +
>> + clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
>> + if (!clk_data)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
>> + ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
>> + clk_data);
>> + if (ret)
>> + return ERR_PTR(ret);
>> +
>> + ret = of_clk_add_provider(pdev->dev.of_node,
>> + of_clk_src_onecell_get, &clk_data->clk_data);
>> + if (ret)
>> + goto unregister_gate;
>> +
>> + return clk_data;
>> +
>> +unregister_gate:
>> + hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
>> + ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
>> + clk_data);
>> + return ERR_PTR(ret);
>> +}
>> +
>> +static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
>> +{
>> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
>> +
>> + of_clk_del_provider(pdev->dev.of_node);
>> +
>> + hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
>> + ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
>> + crg->clk_data);
>> +}
>> +
>> +static struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
>
> const?
>
>> + .register_clks = hi3798cv200_sysctrl_clk_register,
>> + .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
>> +};
>> +
>> +static const struct of_device_id hi3798cv200_crg_match_table[] = {
>> + { .compatible = "hisilicon,hi3798cv200-crg",
>> + .data = &hi3798cv200_crg_funcs},
>
> Nitpick: please add a space before }
>
>> + { .compatible = "hisilicon,hi3798cv200-sysctrl",
>> + .data = &hi3798cv200_sysctrl_funcs},
>
> Nitpick: please add a space before }
>
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, hi3798cv200_clk_match_table);
>> +
>> +static int hi3798cv200_crg_probe(struct platform_device *pdev)
>> +{
>> + struct hisi_crg_dev *crg;
>> + const struct of_device_id *match;
>> +
>> + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
>> + if (!crg)
>> + return -ENOMEM;
>> +
>> + match = of_match_node(hi3798cv200_crg_match_table, pdev->dev.of_node);
>> + crg->funcs = (struct hisi_crg_funcs *)match->data;
>
> We can use of_device_get_match_data() here to simplify things.
>
>> +
>> + crg->rstc = hisi_reset_init(pdev);
>> + if (!crg->rstc)
>> + return -ENOMEM;
>> +
>> diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
>> new file mode 100644
>> index 0000000..145b929
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/crg.h
>> @@ -0,0 +1,39 @@
>> +/*
>> + * HiSilicon Clock and Reset Driver Header
>> + *
>> + * Copyright (c) 2016 HiSilicon Limited.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, write to the Free Software Foundation, Inc.,
>> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>> + *
>> + */
>> +
>> +#ifndef __HISI_CRG_H
>> +#define __HISI_CRG_H
>
> Weird tab here. Please replace with space.
>
>> +
>> +struct hisi_clock_data;
>> +struct hisi_reset_controller;
>> +
>> +struct hisi_crg_funcs {
>> + struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
>> + void (*unregister_clks)(struct platform_device *pdev);
>> +};
>> +
>> +struct hisi_crg_dev {
>> + struct hisi_clock_data *clk_data;
>> + struct hisi_reset_controller *rstc;
>> + struct hisi_crg_funcs *funcs;
>> +};
>> +
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-09-18 1:50 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-12 9:01 [PATCH] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Jiancheng Xue
2016-09-12 13:55 ` kbuild test robot
2016-09-13 2:45 ` Jiancheng Xue
2016-09-14 21:01 ` Stephen Boyd
2016-09-18 1:49 ` Jiancheng Xue
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