From: Andy Gross <andy.gross@linaro.org>
To: Iaroslav Gridin <voker57@gmail.com>
Cc: david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com,
linux@armlinux.org.uk, linux-arm-msm@vger.kernel.org,
linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: msm8974: Add definitions for QCE & cryptobam
Date: Fri, 16 Sep 2016 13:50:12 -0500 [thread overview]
Message-ID: <20160916185012.GC5431@hector.attlocal.net> (raw)
In-Reply-To: <20160916173800.r264xg5wqmer77wr@localhost>
On Fri, Sep 16, 2016 at 08:38:01PM +0300, Iaroslav Gridin wrote:
> On Thu, Sep 15, 2016 at 04:18:42PM -0500, Andy Gross wrote:
>
> > Actually, on thinking about this more, the bam block itself only requires the
> > single clock. The peripheral it is attached to has to keep its sanity during
> > the duration of the transfer (crypto). The crypto requires 3 clocks, one of
> > which is the same clk the bam requires.
> >
> > You can access the BAM registers with the bam_clk only, correct?
>
> Not preparing bam_clk degrades QCE performance about 3x, though.
If the CE2_CLK is the only required clk, that makes it the "bam_clk". I see the
crypto requires getting all three clocks: AXI (bus), AHB (iface), and CE2 (core)
If the crypto is active during DMA transfers, which it has to be, then the
performance shouldn't degrade due to the BAM not preparing the AHB.
Regards,
Andy
prev parent reply other threads:[~2016-09-16 18:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-30 15:37 [PATCH] ARM: dts: msm8974: Add definitions for QCE & cryptobam Iaroslav Gridin
2016-09-07 13:09 ` Stanimir Varbanov
2016-09-07 16:20 ` Iaroslav Gridin
2016-09-17 0:10 ` Stephen Boyd
2016-09-13 3:51 ` Bjorn Andersson
2016-09-15 21:18 ` Andy Gross
2016-09-16 11:59 ` Iaroslav Gridin
2016-09-16 17:38 ` Iaroslav Gridin
2016-09-16 18:50 ` Andy Gross [this message]
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