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Date: Mon, 10 Oct 2016 09:45:44 -0700
From: "Luck, Tony" <tony.luck@intel.com>
To: Nilay Vaish <nilayvaish@gmail.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        "H. Peter Anvin" <h.peter.anvin@intel.com>,
        Ingo Molnar <mingo@elte.hu>, Peter Zijlstra <peterz@infradead.org>,
        Stephane Eranian <eranian@google.com>, Borislav Petkov <bp@suse.de>,
        Dave Hansen <dave.hansen@intel.com>, Shaohua Li <shli@fb.com>,
        David Carrillo-Cisneros <davidcc@google.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        Sai Prakhya <sai.praneeth.prakhya@intel.com>,
        Vikas Shivappa <vikas.shivappa@linux.intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for
 cache id
Message-ID: <20161010164543.GA30442@intel.com>
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On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote:
> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
> > From: Fenghua Yu <fenghua.yu@intel.com>

> > +               caches typically exist per core, but there may not be a
> > +               power of two cores on a socket, so these caches may be
> > +               numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
> > +
> 
> While it is ok that the caches are not numbered contiguously, it is
> unclear how this is related to number of cores on a socket being a
> power of 2 or not.

That's a side effect of the x86 algorithm to generate the unique ID
which uses a shift to put the socket number in some upper bits while
leaving the "id within a socket" in the low bits.

I don't think it worth documenting here, but I noticed that we don't
keep the IDs within a core contguous either.  On my 24 core Broadwell
they are not 0 ... 23 then a gap from 24 to 31.  I actually have on
socket 0:

 0,  1,  2,  3,  4,  5
 8,  9, 10, 11, 12, 13
16, 17, 18, 19, 20, 21
24, 25, 26, 27, 28, 29

-Tony