From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765235AbcJaK1L (ORCPT ); Mon, 31 Oct 2016 06:27:11 -0400 Received: from mail-wm0-f52.google.com ([74.125.82.52]:36141 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764525AbcJaK1I (ORCPT ); Mon, 31 Oct 2016 06:27:08 -0400 Date: Mon, 31 Oct 2016 11:26:59 +0100 From: Daniel Lezcano To: Noam Camus Cc: robh+dt@kernel.org, mark.rutland@arm.com, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/3] soc: Support for NPS HW scheduling Message-ID: <20161031102659.GA1506@mai> References: <1477224748-25223-1-git-send-email-noamca@mellanox.com> <1477224748-25223-2-git-send-email-noamca@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1477224748-25223-2-git-send-email-noamca@mellanox.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Oct 23, 2016 at 03:12:26PM +0300, Noam Camus wrote: > From: Noam Camus > > This new header file is for NPS400 SoC (part of ARC architecture). > The header file includes macros for save/restore of HW scheduling. > The control of HW scheduling is acheived by writing core registers. s/acheived/achieved/ > This code was moved from arc/plat-eznps so it can be used > from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT. > > Signed-off-by: Noam Camus > --- > arch/arc/plat-eznps/include/plat/ctop.h | 2 - > include/soc/nps/mtm.h | 59 +++++++++++++++++++++++++++++++ > 2 files changed, 59 insertions(+), 2 deletions(-) > create mode 100644 include/soc/nps/mtm.h > > diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h > index 9d6718c..ee2e32d 100644 > --- a/arch/arc/plat-eznps/include/plat/ctop.h > +++ b/arch/arc/plat-eznps/include/plat/ctop.h > @@ -46,9 +46,7 @@ > #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) > > /* EZchip core instructions */ > -#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF > #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF > -#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 > #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 > #define CTOP_INST_SCHD_RW 0x3E6F7004 > #define CTOP_INST_SCHD_RD 0x3E6F7084 > diff --git a/include/soc/nps/mtm.h b/include/soc/nps/mtm.h > new file mode 100644 > index 0000000..d2f5e7e > --- /dev/null > +++ b/include/soc/nps/mtm.h > @@ -0,0 +1,59 @@ > +/* > + * Copyright (c) 2016, Mellanox Technologies. All rights reserved. > + * > + * This software is available to you under a choice of one of two > + * licenses. You may choose to be licensed under the terms of the GNU > + * General Public License (GPL) Version 2, available from the file > + * COPYING in the main directory of this source tree, or the > + * OpenIB.org BSD license below: > + * > + * Redistribution and use in source and binary forms, with or > + * without modification, are permitted provided that the following > + * conditions are met: > + * > + * - Redistributions of source code must retain the above > + * copyright notice, this list of conditions and the following > + * disclaimer. > + * > + * - Redistributions in binary form must reproduce the above > + * copyright notice, this list of conditions and the following > + * disclaimer in the documentation and/or other materials > + * provided with the distribution. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS > + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN > + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN > + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE > + * SOFTWARE. > + */ > + > +#ifndef SOC_NPS_MTM_H > +#define SOC_NPS_MTM_H > + > +#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF > +#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 > + > +static inline void hw_schd_save(unsigned int *flags) > +{ > + __asm__ __volatile__( > + " .word %1\n" > + " st r3,[%0]\n" > + : > + : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3) > + : "r3", "memory"); > +} > + Wouldn't make sense to change the macro name to CTOP_INST_HWSCHD_SAVE_R3 ? > +static inline void hw_schd_restore(unsigned int flags) > +{ > + __asm__ __volatile__( > + " mov r3, %0\n" > + " .word %1\n" > + : > + : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3) > + : "r3"); > +} > + > +#endif /* SOC_NPS_MTM_H */ > -- > 1.7.1 >