From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1168376AbcKAJ7J (ORCPT ); Tue, 1 Nov 2016 05:59:09 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:52038 "EHLO outils.crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1168237AbcKAJ7F (ORCPT ); Tue, 1 Nov 2016 05:59:05 -0400 From: Paul Cercueil To: Michael Turquette , Stephen Boyd , Harvey Hunt , Paul Burton , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Maarten ter Huurne , Paul Cercueil Subject: [PATCH] clk: ingenic: Fix recalc_rate for clocks with fixed divider Date: Tue, 1 Nov 2016 10:58:36 +0100 Message-Id: <20161101095836.22210-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index e8248f9..eb9002c 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) div *= clk_info->div.div; rate /= div; + } else if (clk_info->type & CGU_CLK_FIXDIV) { + rate /= clk_info->fixdiv.div; } return rate; -- 2.10.1