From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753877AbcKIS5m (ORCPT ); Wed, 9 Nov 2016 13:57:42 -0500 Received: from foss.arm.com ([217.140.101.70]:33664 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751685AbcKIS5l (ORCPT ); Wed, 9 Nov 2016 13:57:41 -0500 Date: Wed, 9 Nov 2016 18:57:43 +0000 From: Will Deacon To: "Paul E. McKenney" Cc: Andy Lutomirski , Chris Metcalf , Gilad Ben Yossef , Steven Rostedt , Ingo Molnar , Peter Zijlstra , Andrew Morton , Rik van Riel , Tejun Heo , Frederic Weisbecker , Thomas Gleixner , Christoph Lameter , Viresh Kumar , Catalin Marinas , Daniel Lezcano , Francis Giraldeau , Andi Kleen , Arnd Bergmann , "linux-kernel@vger.kernel.org" Subject: Re: task isolation discussion at Linux Plumbers Message-ID: <20161109185743.GN17771@arm.com> References: <1471382376-5443-1-git-send-email-cmetcalf@mellanox.com> <1605b087-2b3b-77c1-01ac-084e378f5f28@mellanox.com> <20161109014045.GI4127@linux.vnet.ibm.com> <20161109173808.GJ4127@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161109173808.GJ4127@linux.vnet.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, Just a couple of comments, but they be more suited to Andy. On Wed, Nov 09, 2016 at 09:38:08AM -0800, Paul E. McKenney wrote: > @@ -355,10 +373,33 @@ static bool rcu_dynticks_in_eqs_since(struct rcu_dynticks *rdtp, int snap) > static void rcu_dynticks_momentary_idle(void) > { > struct rcu_dynticks *rdtp = this_cpu_ptr(&rcu_dynticks); > - int special = atomic_add_return(2, &rdtp->dynticks); > + int special = atomic_add_return(2 * RCU_DYNTICK_CTRL_CTR, > + &rdtp->dynticks); > > /* It is illegal to call this from idle state. */ > - WARN_ON_ONCE(!(special & 0x1)); > + WARN_ON_ONCE(!(special & RCU_DYNTICK_CTRL_CTR)); > +} > + > +/* > + * Set the special (bottom) bit of the specified CPU so that it > + * will take special action (such as flushing its TLB) on the > + * next exit from an extended quiescent state. Returns true if > + * the bit was successfully set, or false if the CPU was not in > + * an extended quiescent state. > + */ Given that TLB maintenance on arm is handled in hardware (no need for IPI), I'd like to avoid this work if at all possible. However, without seeing the call site I can't tell if it's optional. > +bool rcu_eqs_special_set(int cpu) > +{ > + int old; > + int new; > + struct rcu_dynticks *rdtp = &per_cpu(rcu_dynticks, cpu); > + > + do { > + old = atomic_read(&rdtp->dynticks); > + if (old & RCU_DYNTICK_CTRL_CTR) > + return false; > + new = old | RCU_DYNTICK_CTRL_MASK; > + } while (atomic_cmpxchg(&rdtp->dynticks, old, new) != old); > + return true; > } Can this be a cmpxchg_relaxed? What is it attempting to order? Will