From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422693AbcKQGqd (ORCPT ); Thu, 17 Nov 2016 01:46:33 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36110 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422653AbcKQGqa (ORCPT ); Thu, 17 Nov 2016 01:46:30 -0500 Date: Thu, 17 Nov 2016 07:46:26 +0100 From: Ingo Molnar To: Janakarajan Natarajan Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Suravee Suthikulpanit Subject: Re: [PATCH] Support for perf on AMD family17h processors Message-ID: <20161117064625.GA3760@gmail.com> References: <1479315713-11115-1-git-send-email-Janakarajan.Natarajan@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1479315713-11115-1-git-send-email-Janakarajan.Natarajan@amd.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Janakarajan Natarajan wrote: > This patch enables perf core PMU support for AMD family17h processors. In > family17h, there is no PMC-event constraint. All events, irrespective of the > type, can be measured using any of the performance counters. BTW., that's a very nice hardware design that simplifies counter constraints and scheduling! Does Fam17h have 6 generic counters per core, like Fam15h? Thanks, Ingo