From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932785AbcKQJJo (ORCPT ); Thu, 17 Nov 2016 04:09:44 -0500 Received: from mga05.intel.com ([192.55.52.43]:14109 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752910AbcKQJJj (ORCPT ); Thu, 17 Nov 2016 04:09:39 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,504,1473145200"; d="scan'208";a="192459877" Date: Thu, 17 Nov 2016 11:05:14 +0200 From: Mika Westerberg To: Andy Shevchenko Cc: Lee Jones , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate Message-ID: <20161117090514.GM1446@lahna.fi.intel.com> References: <20161115103704.93476-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161115103704.93476-1-andriy.shevchenko@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.7.1 (2016-10-04) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 15, 2016 at 12:37:04PM +0200, Andy Shevchenko wrote: > Enable MWI mechanism if PCI bus master supports it. > > It might be potential benefit in some cases. Documentation [1] says that > standard Memory Write might supply more current data than in the CPU modified > cache line and "trashing a line in the cache may trash some data that is more > current that in the memory line". This allows to avoid potential retries and > other performance degradation issues on the bus. > > [1] PCI System Architecture, 4th edition, ISBN: 0-201-30974-2, pp.117-119. > > Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg