From: Lee Jones <lee.jones@linaro.org>
To: Andrew Jeffery <andrew@aj.id.au>, arnd@arndb.de
Cc: Linus Walleij <linus.walleij@linaro.org>,
Joel Stanley <joel@jms.id.au>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
Date: Fri, 18 Nov 2016 18:45:35 +0000 [thread overview]
Message-ID: <20161118184535.GE19884@dell.home> (raw)
In-Reply-To: <20161118184437.GD19884@dell.home>
[Sending Arnd this time!]
> Arnd,
>
> Do you have a preference?
>
> > The Aspeed LPC Host Controller is presented as a syscon device to
> > arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on
> > fifth generation SoCs depends on bits in both the System Control Unit
> > and the LPC Host Controller.
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++
>
> Create a new directory in bindings/mfd called 'syscon'.
>
> Or perhaps 'bindings/syscon'.
>
> > 1 file changed, 17 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> > new file mode 100644
> > index 000000000000..792651488c3d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
> > @@ -0,0 +1,17 @@
> > +* Device tree bindings for the Aspeed LPC Host Controller (LPCHC)
> > +
> > +The LPCHC registers configure LPC behaviour between the BMC and the host
> > +system. The LPCHC also participates in pinmux requests on g5 SoCs and is
> > +therefore considered a syscon device.
> > +
> > +Required properties:
> > +- compatible: "aspeed,ast2500-lpchc", "syscon"
> > +- reg: contains offset/length value of the LPCHC memory
> > + region.
>
> Why not just use a single tab, then you don't have to linewrap?
>
> > +Example:
> > +
> > +lpchc: lpchc@1e7890a0 {
> > + compatible = "aspeed,ast2500-lpchc", "syscon";
> > + reg = <0x1e7890a0 0xc4>;
> > +};
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
next prev parent reply other threads:[~2016-11-18 18:42 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-02 14:37 [PATCH v2 0/6] pinctrl: aspeed: Fixes for g5, implement remaining pins Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6] Andrew Jeffery
2016-11-03 22:59 ` Joel Stanley
2016-11-07 9:34 ` Linus Walleij
2016-11-07 22:42 ` Andrew Jeffery
2016-11-07 9:32 ` Linus Walleij
2016-11-02 14:37 ` [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-10 3:19 ` Joel Stanley
2016-11-10 17:40 ` Rob Herring
2016-11-18 18:47 ` Lee Jones
2016-11-02 14:37 ` [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC) Andrew Jeffery
2016-11-03 23:06 ` Joel Stanley
2016-11-04 3:45 ` Andrew Jeffery
2016-11-18 18:44 ` Lee Jones
2016-11-18 18:45 ` Lee Jones [this message]
2016-11-22 3:25 ` Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers Andrew Jeffery
2016-11-03 23:24 ` Joel Stanley
2016-11-04 3:59 ` Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-09 23:50 ` Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 5/6] pinctrl: aspeed-g4: Add mux configuration for all pins Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 6/6] pinctrl: aspeed-g5: " Andrew Jeffery
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