From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965137AbcKWOs5 (ORCPT ); Wed, 23 Nov 2016 09:48:57 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:33480 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964884AbcKWOsQ (ORCPT ); Wed, 23 Nov 2016 09:48:16 -0500 From: Magnus Damm To: devicetree@vger.kernel.org, Magnus Damm Cc: mark.rutland@arm.com, laurent.pinchart+renesas@ideasonboard.com, geert+renesas@glider.be, joro@8bytes.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, iommu@lists.linux-foundation.org, robh+dt@kernel.org, horms+renesas@verge.net.au, Magnus Damm Date: Wed, 23 Nov 2016 23:40:54 +0900 Message-Id: <20161123144054.11919.22936.sendpatchset@little-apple> Subject: [PATCH v3] iommu/ipmmu-vmsa: Add r8a7796 DT binding Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Update the IPMMU DT binding documentation to include the r8a7796 compat string for R-Car M3-W. Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart Acked-by: Rob Herring Acked-by: Simon Horman --- This particular patch seems ready to merge IMO. How to proceed? Changes since V2: - Added Acked-by from Rob Herring and Simon Horman - thanks! Changes since V1: - Added Acked-by from Laurent - thanks! Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 1 + 1 file changed, 1 insertion(+) --- 0001/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt +++ work/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt 2016-06-06 11:27:37.560607110 +0900 @@ -16,6 +16,7 @@ Required Properties: - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU. - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU. + - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU. - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU. - reg: Base address and size of the IPMMU registers.