From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756238AbcK2ShM (ORCPT ); Tue, 29 Nov 2016 13:37:12 -0500 Received: from mga09.intel.com ([134.134.136.24]:43605 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753243AbcK2ShF (ORCPT ); Tue, 29 Nov 2016 13:37:05 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,570,1473145200"; d="scan'208";a="1092190517" Date: Tue, 29 Nov 2016 10:37:03 -0800 From: Andi Kleen To: Peter Zijlstra Cc: Stephane Eranian , "Liang, Kan" , "mingo@redhat.com" , LKML , Alexander Shishkin , "Odzioba, Lukasz" Subject: Re: [PATCH] perf/x86: fix event counter update issue Message-ID: <20161129183703.GC8388@tassilo.jf.intel.com> References: <1480361206-1702-1-git-send-email-kan.liang@intel.com> <20161129092520.GB3092@twins.programming.kicks-ass.net> <20161129173055.GP3092@twins.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161129173055.GP3092@twins.programming.kicks-ass.net> User-Agent: Mutt/1.7.1 (2016-10-04) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 29, 2016 at 06:30:55PM +0100, Peter Zijlstra wrote: > On Tue, Nov 29, 2016 at 09:20:10AM -0800, Stephane Eranian wrote: > > Max period is limited by the number of bits the kernel can write to an MSR. > > Used to be 31, now it is 47 for core PMU as per patch pointed to by Kan. > > No, I think it sets it to 48 now, which is the problem. It should be 1 > bit less than the total width. > > So something like so. That looks good. Kan can you test it? -Andi > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index a74a2dbc0180..cb8522290e6a 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) > > /* Support full width counters using alternative MSR range */ > if (x86_pmu.intel_cap.full_width_write) { > - x86_pmu.max_period = x86_pmu.cntval_mask; > + x86_pmu.max_period = x86_pmu.cntval_mask >> 1; > x86_pmu.perfctr = MSR_IA32_PMC0; > pr_cont("full-width counters, "); > }