From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932629AbcLIAO0 (ORCPT ); Thu, 8 Dec 2016 19:14:26 -0500 Received: from mga05.intel.com ([192.55.52.43]:60621 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753113AbcLIAOZ (ORCPT ); Thu, 8 Dec 2016 19:14:25 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,322,1477983600"; d="scan'208";a="38395294" From: Andi Kleen To: peterz@infradead.org Cc: linux-kernel@vger.kernel.org, Andi Kleen , alexander.shishkin@intel.com, kan.liang@intel.com, stable@vger.kernel.org Subject: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Date: Thu, 8 Dec 2016 16:14:17 -0800 Message-Id: <20161209001417.4713-1-andi@firstfloor.org> X-Mailer: git-send-email 2.9.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen An earlier patch allowed enabling PT and LBR at the same time on Goldmont. However it also allowed enabling BTS and LBR at the same time, which is still not supported. Fix this by bypassing the check only for PT. Marking for stable because this allows crashing kernels. Also should be merged for 4.9. Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") Cc: alexander.shishkin@intel.com Cc: kan.liang@intel.com Cc: v2: Paint bike shed differently. Signed-off-by: Andi Kleen --- arch/x86/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index d0efb5cb1b00..baa1eed55e88 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what) { int i; - if (x86_pmu.lbr_pt_coexist) + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist) return 0; if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { @@ -387,7 +387,7 @@ fail_unlock: void x86_del_exclusive(unsigned int what) { - if (x86_pmu.lbr_pt_coexist) + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist) return; atomic_dec(&x86_pmu.lbr_exclusive[what]); -- 2.9.3