From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
alexander.shishkin@intel.com, kan.liang@intel.com,
stable@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>
Subject: Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
Date: Fri, 9 Dec 2016 16:49:57 +0100 [thread overview]
Message-ID: <20161209154957.GV3124@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20161209001417.4713-1-andi@firstfloor.org>
On Thu, Dec 08, 2016 at 04:14:17PM -0800, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> An earlier patch allowed enabling PT and LBR at the same
> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
>
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
>
> Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
> Cc: alexander.shishkin@intel.com
> Cc: kan.liang@intel.com
> Cc: <stable@vger.kernel.org>
> v2: Paint bike shed differently.
Now, if only you'd also clarified the point I asked about. By
documenting these cases we not only get easier to read code, but can
also verify if the code does what is intended.
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
Changed that to the below, which is more explicit on the what is and is
not allowed. And fixed the definition of lbr_pt_coexist.
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
{
int i;
- if (x86_pmu.lbr_pt_coexist)
+ /*
+ * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+ * LBR and BTS are still mutually exclusive.
+ */
+ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ int x86_add_exclusive(unsigned int what)
void x86_del_exclusive(unsigned int what)
{
- if (x86_pmu.lbr_pt_coexist)
+ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
atomic_dec(&x86_pmu.lbr_exclusive[what]);
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask; /* LBR_SELECT valid bits */
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
- bool lbr_pt_coexist; /* LBR may coexist with PT */
+ bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
/*
* Intel PT/LBR/BTS are exclusive
next prev parent reply other threads:[~2016-12-09 15:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-09 0:14 [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Andi Kleen
2016-12-09 15:49 ` Peter Zijlstra [this message]
2016-12-12 6:49 ` [tip:perf/core] " tip-bot for Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2016-12-02 23:17 [PATCH] " Andi Kleen
2016-12-06 12:38 ` Peter Zijlstra
2016-12-06 14:53 ` Andi Kleen
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