[PATCH 0/4] PCI: exynos: cleans the minor things

[PATCH 0/4] PCI: exynos: cleans the minor things

[Jaehoon Chung]

Current pci-exnoys.c is used for only EXYNOS5440.
Even if there is no use-case, just cleans the codes for maintaining.

In future, I will upstream for Exynso5433(TM2).
Before sending patches for exynos5433, i want to reuse the some codse in pic-exynos.c.
This patch is for perparing it.

My Final goal is to apply the pcie-exynos5433 into v4.11.

Jaehoon Chung (4):
  PCI: exynos: replace to one register accessor from each accessors
  PCI: exynos: Remove the unnecessary variables
  PCI: exynos: Use the bitops API to operate the bit shifting
  PCI: exynos: remove the duplicated codes

 drivers/pci/host/pci-exynos.c | 260 +++++++++++++++++++-----------------------
 1 file changed, 116 insertions(+), 144 deletions(-)

-- 
2.10.2

[PATCH 1/4] PCI: exynos: replace to one register accessor from each accessors

[Jaehoon Chung]

There is no reason to maintain *_blk/phy/elbi_* as register accessors.
It can be replaced to one register accessor.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/pci/host/pci-exynos.c | 214 +++++++++++++++++++-----------------------
 1 file changed, 97 insertions(+), 117 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index f1c544b..6dbfa2c 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -102,197 +102,175 @@ struct exynos_pcie {
 #define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)
 #define PCIE_PHY_TRSV3_LVCC		0x31c
 
-static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
+static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
 {
-	writel(val, exynos_pcie->elbi_base + reg);
+	writel(val, base + reg);
 }
 
-static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)
+static u32 exynos_pcie_readl(void __iomem *base, u32 reg)
 {
-	return readl(exynos_pcie->elbi_base + reg);
+	return readl(base + reg);
 }
 
-static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
-{
-	writel(val, exynos_pcie->phy_base + reg);
-}
-
-static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)
-{
-	return readl(exynos_pcie->phy_base + reg);
-}
-
-static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
-{
-	writel(val, exynos_pcie->block_base + reg);
-}
-
-static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)
-{
-	return readl(exynos_pcie->block_base + reg);
-}
-
-static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie,
-					    bool on)
+static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
 {
 	u32 val;
 
 	if (on) {
-		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
+		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
 		val |= PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
+		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
 	} else {
-		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
+		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
 		val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
+		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
 	}
 }
 
-static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos_pcie,
-					    bool on)
+static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
 {
 	u32 val;
 
 	if (on) {
-		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
+		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
 		val |= PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
+		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
 	} else {
-		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
+		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
 		val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
+		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
 	}
 }
 
-static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
 {
 	u32 val;
 
-	val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
+	val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
 	val &= ~PCIE_CORE_RESET_ENABLE;
-	exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
-	exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
-	exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
-	exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
+	exynos_pcie_writel(ep->elbi_base, 0, PCIE_PWR_RESET);
+	exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
+	exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
 }
 
-static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
 {
 	u32 val;
 
-	val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
+	val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
 	val |= PCIE_CORE_RESET_ENABLE;
 
-	exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
-	exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
-	exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
-	exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
-	exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
-	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
+	exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
+	exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
+	exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
+	exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
+	exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_MAC_RESET);
 }
 
-static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
 {
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
-	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
+	exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_MAC_RESET);
+	exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_GLOBAL_RESET);
 }
 
-static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
 {
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
-	exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
+	exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_GLOBAL_RESET);
+	exynos_pcie_writel(ep->elbi_base, 1, PCIE_PWR_RESET);
+	exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
+	exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_CMN_REG);
+	exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSVREG_RESET);
+	exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSV_RESET);
 }
 
-static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
 {
 	u32 val;
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
 	val &= ~PCIE_PHY_COMMON_PD_CMN;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
 	val &= ~PCIE_PHY_TRSV0_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
 	val &= ~PCIE_PHY_TRSV1_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
 	val &= ~PCIE_PHY_TRSV2_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
 	val &= ~PCIE_PHY_TRSV3_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
 }
 
-static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
 {
 	u32 val;
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
 	val |= PCIE_PHY_COMMON_PD_CMN;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
 	val |= PCIE_PHY_TRSV0_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
 	val |= PCIE_PHY_TRSV1_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
 	val |= PCIE_PHY_TRSV2_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
 
-	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
+	val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
 	val |= PCIE_PHY_TRSV3_PD_TSV;
-	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
+	exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
 }
 
-static void exynos_pcie_init_phy(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_init_phy(struct exynos_pcie *ep)
 {
 	/* DCC feedback control off */
-	exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
+	exynos_pcie_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
 
 	/* set TX/RX impedance */
-	exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
+	exynos_pcie_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
 
 	/* set 50Mhz PHY clock */
-	exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
-	exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
+	exynos_pcie_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
+	exynos_pcie_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
 
 	/* set TX Differential output for lane 0 */
-	exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+	exynos_pcie_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
 
 	/* set TX Pre-emphasis Level Control for lane 0 to minimum */
-	exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+	exynos_pcie_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
 
 	/* set RX clock and data recovery bandwidth */
-	exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
-	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
-	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
-	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
-	exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
+	exynos_pcie_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
+	exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
+	exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
+	exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
+	exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
 
 	/* change TX Pre-emphasis Level Control for lanes */
-	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
-	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
-	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
-	exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+	exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+	exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+	exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+	exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
 
 	/* set LVCC */
-	exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
-	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
-	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
-	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
+	exynos_pcie_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
+	exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
+	exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
+	exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
 }
 
 static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
@@ -323,46 +301,48 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
 	exynos_pcie_init_phy(exynos_pcie);
 
 	/* pulse for common reset */
-	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
+	exynos_pcie_writel(exynos_pcie->block_base, 1, PCIE_PHY_COMMON_RESET);
 	udelay(500);
-	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
+	exynos_pcie_writel(exynos_pcie->block_base, 0, PCIE_PHY_COMMON_RESET);
 
 	exynos_pcie_deassert_core_reset(exynos_pcie);
 	dw_pcie_setup_rc(pp);
 	exynos_pcie_assert_reset(exynos_pcie);
 
 	/* assert LTSSM enable */
-	exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
+	exynos_pcie_writel(exynos_pcie->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
 			  PCIE_APP_LTSSM_ENABLE);
 
 	/* check if the link is up or not */
 	if (!dw_pcie_wait_for_link(pp))
 		return 0;
 
-	while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
-		val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
+	while (exynos_pcie_readl(exynos_pcie->phy_base,
+				PCIE_PHY_PLL_LOCKED) == 0) {
+		val = exynos_pcie_readl(exynos_pcie->block_base,
+				PCIE_PHY_PLL_LOCKED);
 		dev_info(dev, "PLL Locked: 0x%x\n", val);
 	}
 	exynos_pcie_power_off_phy(exynos_pcie);
 	return -ETIMEDOUT;
 }
 
-static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
 {
 	u32 val;
 
-	val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
-	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
+	val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
 }
 
-static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
 {
 	u32 val;
 
 	/* enable INTX interrupt */
 	val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
 		IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
-	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
 }
 
 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
@@ -381,17 +361,17 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
 	return dw_handle_msi_irq(pp);
 }
 
-static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_msi_init(struct exynos_pcie *ep)
 {
-	struct pcie_port *pp = &exynos_pcie->pp;
+	struct pcie_port *pp = &ep->pp;
 	u32 val;
 
 	dw_pcie_msi_init(pp);
 
 	/* enable MSI interrupt */
-	val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
+	val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_EN_LEVEL);
 	val |= IRQ_MSI_ENABLE;
-	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_LEVEL);
 }
 
 static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
@@ -451,7 +431,7 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
 	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
 	u32 val;
 
-	val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
+	val = exynos_pcie_readl(exynos_pcie->elbi_base, PCIE_ELBI_RDLH_LINKUP);
 	if (val == PCIE_ELBI_LTSSM_ENABLE)
 		return 1;
 
-- 
2.10.2

[PATCH 2/4] PCI: exynos: Remove the unnecessary variables

[Jaehoon Chung]

Remove the unnecessary variables(elbi/phy/block_base).
It needs one resource structure for assigning each resource.
So it replaces with one 'res' variable.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/pci/host/pci-exynos.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 6dbfa2c..d64e8f1 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -509,9 +509,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	struct exynos_pcie *exynos_pcie;
 	struct pcie_port *pp;
 	struct device_node *np = dev->of_node;
-	struct resource *elbi_base;
-	struct resource *phy_base;
-	struct resource *block_base;
+	struct resource *res;
 	int ret;
 
 	exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
@@ -542,22 +540,22 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto fail_clk;
 
-	elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	exynos_pcie->elbi_base = devm_ioremap_resource(dev, elbi_base);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	exynos_pcie->elbi_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(exynos_pcie->elbi_base)) {
 		ret = PTR_ERR(exynos_pcie->elbi_base);
 		goto fail_bus_clk;
 	}
 
-	phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	exynos_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	exynos_pcie->phy_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(exynos_pcie->phy_base)) {
 		ret = PTR_ERR(exynos_pcie->phy_base);
 		goto fail_bus_clk;
 	}
 
-	block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-	exynos_pcie->block_base = devm_ioremap_resource(dev, block_base);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	exynos_pcie->block_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(exynos_pcie->block_base)) {
 		ret = PTR_ERR(exynos_pcie->block_base);
 		goto fail_bus_clk;
-- 
2.10.2

[PATCH 3/4] PCI: exynos: Use the bitops API to operate the bit shifting

[Jaehoon Chung]

Just use the bitops api to operate the bit.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index d64e8f1..d705bfe 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -40,19 +40,19 @@ struct exynos_pcie {
 
 /* PCIe ELBI registers */
 #define PCIE_IRQ_PULSE			0x000
-#define IRQ_INTA_ASSERT			(0x1 << 0)
-#define IRQ_INTB_ASSERT			(0x1 << 2)
-#define IRQ_INTC_ASSERT			(0x1 << 4)
-#define IRQ_INTD_ASSERT			(0x1 << 6)
+#define IRQ_INTA_ASSERT			BIT(0)
+#define IRQ_INTB_ASSERT			BIT(2)
+#define IRQ_INTC_ASSERT			BIT(4)
+#define IRQ_INTD_ASSERT			BIT(6)
 #define PCIE_IRQ_LEVEL			0x004
 #define PCIE_IRQ_SPECIAL		0x008
 #define PCIE_IRQ_EN_PULSE		0x00c
 #define PCIE_IRQ_EN_LEVEL		0x010
-#define IRQ_MSI_ENABLE			(0x1 << 2)
+#define IRQ_MSI_ENABLE			BIT(2)
 #define PCIE_IRQ_EN_SPECIAL		0x014
 #define PCIE_PWR_RESET			0x018
 #define PCIE_CORE_RESET			0x01c
-#define PCIE_CORE_RESET_ENABLE		(0x1 << 0)
+#define PCIE_CORE_RESET_ENABLE		BIT(0)
 #define PCIE_STICKY_RESET		0x020
 #define PCIE_NONSTICKY_RESET		0x024
 #define PCIE_APP_INIT_RESET		0x028
@@ -61,7 +61,7 @@ struct exynos_pcie {
 #define PCIE_ELBI_LTSSM_ENABLE		0x1
 #define PCIE_ELBI_SLV_AWMISC		0x11c
 #define PCIE_ELBI_SLV_ARMISC		0x120
-#define PCIE_ELBI_SLV_DBI_ENABLE	(0x1 << 21)
+#define PCIE_ELBI_SLV_DBI_ENABLE	BIT(21)
 
 /* PCIe Purple registers */
 #define PCIE_PHY_GLOBAL_RESET		0x000
@@ -79,27 +79,27 @@ struct exynos_pcie {
 #define PCIE_PHY_DCC_FEEDBACK		0x014
 #define PCIE_PHY_PLL_DIV_1		0x05c
 #define PCIE_PHY_COMMON_POWER		0x064
-#define PCIE_PHY_COMMON_PD_CMN		(0x1 << 3)
+#define PCIE_PHY_COMMON_PD_CMN		BIT(3)
 #define PCIE_PHY_TRSV0_EMP_LVL		0x084
 #define PCIE_PHY_TRSV0_DRV_LVL		0x088
 #define PCIE_PHY_TRSV0_RXCDR		0x0ac
 #define PCIE_PHY_TRSV0_POWER		0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV		(0x1 << 7)
+#define PCIE_PHY_TRSV0_PD_TSV		BIT(7)
 #define PCIE_PHY_TRSV0_LVCC		0x0dc
 #define PCIE_PHY_TRSV1_EMP_LVL		0x144
 #define PCIE_PHY_TRSV1_RXCDR		0x16c
 #define PCIE_PHY_TRSV1_POWER		0x184
-#define PCIE_PHY_TRSV1_PD_TSV		(0x1 << 7)
+#define PCIE_PHY_TRSV1_PD_TSV		BIT(7)
 #define PCIE_PHY_TRSV1_LVCC		0x19c
 #define PCIE_PHY_TRSV2_EMP_LVL		0x204
 #define PCIE_PHY_TRSV2_RXCDR		0x22c
 #define PCIE_PHY_TRSV2_POWER		0x244
-#define PCIE_PHY_TRSV2_PD_TSV		(0x1 << 7)
+#define PCIE_PHY_TRSV2_PD_TSV		BIT(7)
 #define PCIE_PHY_TRSV2_LVCC		0x25c
 #define PCIE_PHY_TRSV3_EMP_LVL		0x2c4
 #define PCIE_PHY_TRSV3_RXCDR		0x2ec
 #define PCIE_PHY_TRSV3_POWER		0x304
-#define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)
+#define PCIE_PHY_TRSV3_PD_TSV		BIT(7)
 #define PCIE_PHY_TRSV3_LVCC		0x31c
 
 static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
-- 
2.10.2

[PATCH 4/4] PCI: exynos: remove the duplicated codes

[Jaehoon Chung]

Removed the duplicated codes.
It can use the more simply than now.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/pci/host/pci-exynos.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index d705bfe..33562cf 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -116,30 +116,24 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
 {
 	u32 val;
 
-	if (on) {
-		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+	val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+	if (on)
 		val |= PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
-	} else {
-		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+	else
 		val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
-	}
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
 }
 
 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
 {
 	u32 val;
 
-	if (on) {
-		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
+	val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
+	if (on)
 		val |= PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
-	} else {
-		val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
+	else
 		val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
-		exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
-	}
+	exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
 }
 
 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
-- 
2.10.2

Re: [PATCH 0/4] PCI: exynos: cleans the minor things

[Bartlomiej Zolnierkiewicz]

Hi,

On Monday, December 19, 2016 05:16:10 PM Jaehoon Chung wrote:
> Current pci-exnoys.c is used for only EXYNOS5440.
> Even if there is no use-case, just cleans the codes for maintaining.
> 
> In future, I will upstream for Exynso5433(TM2).
> Before sending patches for exynos5433, i want to reuse the some codse in pic-exynos.c.
> This patch is for perparing it.
> 
> My Final goal is to apply the pcie-exynos5433 into v4.11.
> 
> Jaehoon Chung (4):
>   PCI: exynos: replace to one register accessor from each accessors
>   PCI: exynos: Remove the unnecessary variables
>   PCI: exynos: Use the bitops API to operate the bit shifting
>   PCI: exynos: remove the duplicated codes
> 
>  drivers/pci/host/pci-exynos.c | 260 +++++++++++++++++++-----------------------
>  1 file changed, 116 insertions(+), 144 deletions(-)

Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH 0/4] PCI: exynos: cleans the minor things

[Jingoo Han]

On Tuesday, December 20, 2016 12:36 PM, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> On Monday, December 19, 2016 05:16:10 PM Jaehoon Chung wrote:
> > Current pci-exnoys.c is used for only EXYNOS5440.
> > Even if there is no use-case, just cleans the codes for maintaining.
> >
> > In future, I will upstream for Exynso5433(TM2).
> > Before sending patches for exynos5433, i want to reuse the some codse in
> pic-exynos.c.
> > This patch is for perparing it.
> >
> > My Final goal is to apply the pcie-exynos5433 into v4.11.
> >
> > Jaehoon Chung (4):
> >   PCI: exynos: replace to one register accessor from each accessors
> >   PCI: exynos: Remove the unnecessary variables
> >   PCI: exynos: Use the bitops API to operate the bit shifting
> >   PCI: exynos: remove the duplicated codes
> >
> >  drivers/pci/host/pci-exynos.c | 260 +++++++++++++++++++----------------
> -------
> >  1 file changed, 116 insertions(+), 144 deletions(-)
> 
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> 
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics

Re: [PATCH 1/4] PCI: exynos: replace to one register accessor from each accessors

[Bjorn Helgaas]

Hi Jaehoon,

On Mon, Dec 19, 2016 at 05:16:11PM +0900, Jaehoon Chung wrote:
> There is no reason to maintain *_blk/phy/elbi_* as register accessors.
> It can be replaced to one register accessor.
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
>  drivers/pci/host/pci-exynos.c | 214 +++++++++++++++++++-----------------------
>  1 file changed, 97 insertions(+), 117 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index f1c544b..6dbfa2c 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -102,197 +102,175 @@ struct exynos_pcie {
>  #define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)
>  #define PCIE_PHY_TRSV3_LVCC		0x31c
>  
> -static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
> +static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
>  {
> -	writel(val, exynos_pcie->elbi_base + reg);
> +	writel(val, base + reg);
>  }
>  
> -static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)
> +static u32 exynos_pcie_readl(void __iomem *base, u32 reg)
>  {
> -	return readl(exynos_pcie->elbi_base + reg);
> +	return readl(base + reg);
>  }
>  
> -static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
> -{
> -	writel(val, exynos_pcie->phy_base + reg);
> -}
> -
> -static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)
> -{
> -	return readl(exynos_pcie->phy_base + reg);
> -}
> -
> -static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
> -{
> -	writel(val, exynos_pcie->block_base + reg);
> -}
> -
> -static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)
> -{
> -	return readl(exynos_pcie->block_base + reg);
> -}
> -
> -static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie,
> -					    bool on)
> +static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)

Replacing all the separate accessors with one that takes the base
pointer is OK, but please use the same name for all the "struct
exynos_pcie *" pointers in the whole file.

Before your patch, they were all called "exynos_pci"; after it some
are called "exynos_pci" and some are called "ep".

Bjorn

Re: [PATCH 1/4] PCI: exynos: replace to one register accessor from each accessors

[Jaehoon Chung]

Hi Bjorn,

On 01/12/2017 03:50 AM, Bjorn Helgaas wrote:
> Hi Jaehoon,
> 
> On Mon, Dec 19, 2016 at 05:16:11PM +0900, Jaehoon Chung wrote:
>> There is no reason to maintain *_blk/phy/elbi_* as register accessors.
>> It can be replaced to one register accessor.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>>  drivers/pci/host/pci-exynos.c | 214 +++++++++++++++++++-----------------------
>>  1 file changed, 97 insertions(+), 117 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>> index f1c544b..6dbfa2c 100644
>> --- a/drivers/pci/host/pci-exynos.c
>> +++ b/drivers/pci/host/pci-exynos.c
>> @@ -102,197 +102,175 @@ struct exynos_pcie {
>>  #define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)
>>  #define PCIE_PHY_TRSV3_LVCC		0x31c
>>  
>> -static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
>> +static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
>>  {
>> -	writel(val, exynos_pcie->elbi_base + reg);
>> +	writel(val, base + reg);
>>  }
>>  
>> -static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)
>> +static u32 exynos_pcie_readl(void __iomem *base, u32 reg)
>>  {
>> -	return readl(exynos_pcie->elbi_base + reg);
>> +	return readl(base + reg);
>>  }
>>  
>> -static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
>> -{
>> -	writel(val, exynos_pcie->phy_base + reg);
>> -}
>> -
>> -static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)
>> -{
>> -	return readl(exynos_pcie->phy_base + reg);
>> -}
>> -
>> -static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
>> -{
>> -	writel(val, exynos_pcie->block_base + reg);
>> -}
>> -
>> -static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)
>> -{
>> -	return readl(exynos_pcie->block_base + reg);
>> -}
>> -
>> -static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie,
>> -					    bool on)
>> +static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
> 
> Replacing all the separate accessors with one that takes the base
> pointer is OK, but please use the same name for all the "struct
> exynos_pcie *" pointers in the whole file.
> 
> Before your patch, they were all called "exynos_pci"; after it some
> are called "exynos_pci" and some are called "ep".

I will use the 'ep' as name, exynos_pcie is a little bit long.
When 'exynos_pcie' is used, some code is need to change lines because of 80 char.
I think it's the meaningless line changing.

I will resend the PATCH v2..also patches relevant to using PHY framework.
After applying everything, i will upstream TM2(Exynos5433) PCIe patches.

Thanks for reviewing.

Best Regards,
Jaehoon Chung

> 
> Bjorn
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

Re: [PATCH 2/4] PCI: exynos: Remove the unnecessary variables

[Krzysztof Kozlowski]

On Mon, Dec 19, 2016 at 05:17:38PM +0900, Jaehoon Chung wrote:
> Remove the unnecessary variables(elbi/phy/block_base).
> It needs one resource structure for assigning each resource.
> So it replaces with one 'res' variable.
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
>  drivers/pci/host/pci-exynos.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH 2/4] PCI: exynos: Remove the unnecessary variables

[Jaehoon Chung]

Remove the unnecessary variables(elbi/phy/block_base).
It needs one resource structure for assigning each resource.
So it replaces with one 'res' variable.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/pci/host/pci-exynos.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 6dbfa2c..d64e8f1 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -509,9 +509,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	struct exynos_pcie *exynos_pcie;
 	struct pcie_port *pp;
 	struct device_node *np = dev->of_node;
-	struct resource *elbi_base;
-	struct resource *phy_base;
-	struct resource *block_base;
+	struct resource *res;
 	int ret;
 
 	exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
@@ -542,22 +540,22 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto fail_clk;
 
-	elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	exynos_pcie->elbi_base = devm_ioremap_resource(dev, elbi_base);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	exynos_pcie->elbi_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(exynos_pcie->elbi_base)) {
 		ret = PTR_ERR(exynos_pcie->elbi_base);
 		goto fail_bus_clk;
 	}
 
-	phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	exynos_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	exynos_pcie->phy_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(exynos_pcie->phy_base)) {
 		ret = PTR_ERR(exynos_pcie->phy_base);
 		goto fail_bus_clk;
 	}
 
-	block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-	exynos_pcie->block_base = devm_ioremap_resource(dev, block_base);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	exynos_pcie->block_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(exynos_pcie->block_base)) {
 		ret = PTR_ERR(exynos_pcie->block_base);
 		goto fail_bus_clk;
-- 
2.10.2