From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932717AbcLSIQ6 (ORCPT ); Mon, 19 Dec 2016 03:16:58 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:39068 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754807AbcLSIQY (ORCPT ); Mon, 19 Dec 2016 03:16:24 -0500 X-AuditID: cbfee61a-f79bd6d000000fc6-9a-585797502214 From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: helgaas@google.com, krzk@kernel.org, linux-kernel@vger.kernel.org, jingoohan1@gmail.com, javier@osg.samsung.com, kgene@kernel.org, linux-samsung-soc@vger.kernel.org, Jaehoon Chung Subject: [PATCH 3/4] PCI: exynos: Use the bitops API to operate the bit shifting Date: Mon, 19 Dec 2016 17:16:13 +0900 Message-id: <20161219081614.5403-4-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20161219081614.5403-1-jh80.chung@samsung.com> References: <20161219081614.5403-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsVy+t9jQd2A6eERBnvPWFvMer6H1eLN2zVM Fjd+tbFarPgyk92i//FrZovz5zewW1zeNYfN4uy842wWM87vY3Lg9Ng56y67x4JNpR6bVnWy eWzpB/L6tqxi9Pi8SS6ALcrNJiM1MSW1SCE1Lzk/JTMv3VYpNMRN10JJIS8xN9VWKULXNyRI SaEsMacUyDMyQAMOzgHuwUr6dgluGW1LbrIUtIlXfFt1ma2BcYlwFyMnh4SAicSZvT9ZIWwx iQv31rN1MXJxCAnMYpR423SEBcL5wShxpX0WG0gVm4COxPZvx5lAbBEBWYmPl/eAdTALXGGU eDr3AFAHB4ewQIDE/u2KICaLgKrEzCOOIOW8AlYSWx/PYIJYJi+x8PwRMJtTwFpi4uIPzCC2 EFDN2tUXmCcw8i5gZFjFKJFakFxQnJSea5iXWq5XnJhbXJqXrpecn7uJERzuz6R2MB7c5X6I UYCDUYmHt+B9WIQQa2JZcWXuIUYJDmYlEV7HyeERQrwpiZVVqUX58UWlOanFhxhNge6ayCwl mpwPjMW8knhDE3MTc2MDC3NLSxMjJXHextnPwoUE0hNLUrNTUwtSi2D6mDg4pRoYT2esm+73 edsBrS2TfLIVPXP3Ljh/9ERDgn208rfPlgtFpf9fZWn8mVgZIqb3uiZz8eOUE7van1+8EZZe M+t+p8oPS6cNkVdTNDUX8rl+iV+2+7QB65wYne4XT00YVLTlmQrbTSrn1Wbbxc1zyrb8W/Tz w+S6tz8WlH3beVW2VXd/1CHFzw+XKLEUZyQaajEXFScCAKex/bGNAgAA X-MTR: 20000000000000000@CPGS Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Just use the bitops api to operate the bit. Signed-off-by: Jaehoon Chung --- drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index d64e8f1..d705bfe 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -40,19 +40,19 @@ struct exynos_pcie { /* PCIe ELBI registers */ #define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT (0x1 << 0) -#define IRQ_INTB_ASSERT (0x1 << 2) -#define IRQ_INTC_ASSERT (0x1 << 4) -#define IRQ_INTD_ASSERT (0x1 << 6) +#define IRQ_INTA_ASSERT BIT(0) +#define IRQ_INTB_ASSERT BIT(2) +#define IRQ_INTC_ASSERT BIT(4) +#define IRQ_INTD_ASSERT BIT(6) #define PCIE_IRQ_LEVEL 0x004 #define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 -#define IRQ_MSI_ENABLE (0x1 << 2) +#define IRQ_MSI_ENABLE BIT(2) #define PCIE_IRQ_EN_SPECIAL 0x014 #define PCIE_PWR_RESET 0x018 #define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE (0x1 << 0) +#define PCIE_CORE_RESET_ENABLE BIT(0) #define PCIE_STICKY_RESET 0x020 #define PCIE_NONSTICKY_RESET 0x024 #define PCIE_APP_INIT_RESET 0x028 @@ -61,7 +61,7 @@ struct exynos_pcie { #define PCIE_ELBI_LTSSM_ENABLE 0x1 #define PCIE_ELBI_SLV_AWMISC 0x11c #define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) /* PCIe Purple registers */ #define PCIE_PHY_GLOBAL_RESET 0x000 @@ -79,27 +79,27 @@ struct exynos_pcie { #define PCIE_PHY_DCC_FEEDBACK 0x014 #define PCIE_PHY_PLL_DIV_1 0x05c #define PCIE_PHY_COMMON_POWER 0x064 -#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) +#define PCIE_PHY_COMMON_PD_CMN BIT(3) #define PCIE_PHY_TRSV0_EMP_LVL 0x084 #define PCIE_PHY_TRSV0_DRV_LVL 0x088 #define PCIE_PHY_TRSV0_RXCDR 0x0ac #define PCIE_PHY_TRSV0_POWER 0x0c4 -#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV0_PD_TSV BIT(7) #define PCIE_PHY_TRSV0_LVCC 0x0dc #define PCIE_PHY_TRSV1_EMP_LVL 0x144 #define PCIE_PHY_TRSV1_RXCDR 0x16c #define PCIE_PHY_TRSV1_POWER 0x184 -#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV1_PD_TSV BIT(7) #define PCIE_PHY_TRSV1_LVCC 0x19c #define PCIE_PHY_TRSV2_EMP_LVL 0x204 #define PCIE_PHY_TRSV2_RXCDR 0x22c #define PCIE_PHY_TRSV2_POWER 0x244 -#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV2_PD_TSV BIT(7) #define PCIE_PHY_TRSV2_LVCC 0x25c #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 #define PCIE_PHY_TRSV3_RXCDR 0x2ec #define PCIE_PHY_TRSV3_POWER 0x304 -#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV3_PD_TSV BIT(7) #define PCIE_PHY_TRSV3_LVCC 0x31c static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) -- 2.10.2