From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761814AbcLSQba (ORCPT ); Mon, 19 Dec 2016 11:31:30 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:34317 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754938AbcLSQb2 (ORCPT ); Mon, 19 Dec 2016 11:31:28 -0500 Date: Mon, 19 Dec 2016 10:31:26 -0600 From: Rob Herring To: Anurup M Cc: mark.rutland@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com, tanxiaojun@huawei.com, xuwei5@hisilicon.com, sanil.kumar@hisilicon.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, shiju.jose@huawei.com, wangkefeng.wang@huawei.com, linuxarm@huawei.com, shyju.pv@huawei.com Subject: Re: [PATCH v2 02/10] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Djtag dts bindings Message-ID: <20161219163126.w6ibkd6ayvblkwqt@rob-hp-laptop> References: <1481129719-159487-1-git-send-email-anurup.m@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1481129719-159487-1-git-send-email-anurup.m@huawei.com> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 07, 2016 at 11:55:19AM -0500, Anurup M wrote: > From: Tan Xiaojun > > Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die > > Signed-off-by: Tan Xiaojun > Signed-off-by: Anurup M > --- > .../devicetree/bindings/arm/hisilicon/djtag.txt | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/djtag.txt > > diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt > new file mode 100644 > index 0000000..733498e > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt > @@ -0,0 +1,41 @@ > +The Hisilicon Djtag is an independent component which connects with some other > +components in the SoC by Debug Bus. The djtag is available in CPU and IO dies > +in the chip. The djtag controls access to connecting modules of CPU and IO > +dies. > +The various connecting components in CPU die (like L3 cache, L3 cache PMU etc.) > +are accessed by djtag during real time debugging. In IO die there are connecting > +components like RSA. These components appear as devices atatched to djtag bus. > + > +Hisilicon HiP05/06 djtag for CPU and HiP05 IO die > +Required properties: > + - compatible : "hisilicon,hisi-djtag-v1" These need SoC specific compatible strings. They probably should also include cpu or io in the compatible string. I would expect there are things like events, triggers, or component connections for debug that are SoC specifc. > + - reg : Register address and size > + - scl-id : The Super Cluster ID for CPU or IO die > + > +Hisilicon HiP06 djtag for IO die and HiP07 djtag for CPU and IO die > +Required properties: > + - compatible : "hisilicon,hisi-djtag-v2" Same here. > + - reg : Register address and size > + - scl-id : The Super Cluster ID for CPU or IO die > + > +Example 1: Djtag for CPU die > + > + /* for Hisilicon HiP05 djtag for CPU Die */ > + djtag0: djtag@80010000 { > + compatible = "hisilicon,hisi-djtag-v1"; > + reg = <0x0 0x80010000 0x0 0x10000>; > + scl-id = <0x02>; > + > + /* All connecting components will appear as child nodes */ > + }; > + > +Example 2: Djtag for IO die > + > + /* for Hisilicon HiP05 djtag for IO Die */ > + djtag1: djtag@d0000000 { > + compatible = "hisilicon,hisi-djtag-v1"; > + reg = <0x0 0xd0000000 0x0 0x10000>; > + scl-id = <0x01>; > + > + /* All connecting components will appear as child nodes */ > + }; > -- > 2.1.4 >