From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763064AbcLTHQw (ORCPT ); Tue, 20 Dec 2016 02:16:52 -0500 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:56927 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762545AbcLTHQr (ORCPT ); Tue, 20 Dec 2016 02:16:47 -0500 X-ME-Sender: X-Sasl-enc: h2G9CnQOOPgN7IfhsUT6EwZz/OqtkyB8SdJHUWK8Ss3O 1482218206 From: Andrew Jeffery To: Lee Jones Cc: Andrew Jeffery , Rob Herring , Mark Rutland , Linus Walleij , Corey Minyard , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/5] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Date: Tue, 20 Dec 2016 17:45:34 +1030 Message-Id: <20161220071535.27542-5-andrew@aj.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161220071535.27542-1-andrew@aj.id.au> References: <20161220071535.27542-1-andrew@aj.id.au> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux drivers. Signed-off-by: Andrew Jeffery Reviewed-by: Linus Walleij --- Linus: I've retained your r-b tag I don't think the addition of the ast2400 compatible string will fuss you. Please let me know if you feel this is inappropriate. .../devicetree/bindings/mfd/aspeed-lpc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index a97131aba446..514d82ced95b 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -109,3 +109,29 @@ lpc: lpc@1e789000 { }; }; +Host Node Children +================== + +LPC Host Controller +------------------- + +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour +between the host and the baseboard management controller. The registers exist +in the "host" portion of the Aspeed LPC controller, which must be the parent of +the LPC host controller node. + +Required properties: + +- compatible: One of: + "aspeed,ast2400-lhc"; + "aspeed,ast2500-lhc"; + +- reg: contains offset/length values of the LHC memory regions. In the + AST2400 and AST2500 there are two regions. + +Example: + +lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; +}; -- 2.9.3