From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755628AbdABOuU (ORCPT ); Mon, 2 Jan 2017 09:50:20 -0500 Received: from 14.mo5.mail-out.ovh.net ([188.165.51.82]:47840 "EHLO 14.mo5.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755543AbdABOuT (ORCPT ); Mon, 2 Jan 2017 09:50:19 -0500 Date: Mon, 2 Jan 2017 15:44:37 +0100 From: Lukasz Majewski To: Vladimir Zapolskiy Cc: Rob Herring , Mark Rutland , Russell King , Shawn Guo , Fabio Estevam , , , , Sascha Hauer , Lukasz Majewski Subject: Re: [PATCH] DTS: MCCMON6: IMX: Provide support for iMX6Q based Liebherr mccmon6 board Message-ID: <20170102154437.63406b95@jawa> In-Reply-To: <610d3784-ee2e-c213-2a8c-6db6d7af578b@mentor.com> References: <1482794396-16153-1-git-send-email-l.majewski@majess.pl> <610d3784-ee2e-c213-2a8c-6db6d7af578b@mentor.com> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; boundary="Sig_/.0NNA_UA99nYKxyeYOjmUKR"; protocol="application/pgp-signature" X-Ovh-Tracer-Id: 7451487059390808735 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelgedruddugdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Sig_/.0NNA_UA99nYKxyeYOjmUKR Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hi Vladimir, Thank you for review. Comments without my remarks have been applied already. > Hello Lukasz, >=20 > On 12/27/2016 01:19 AM, Lukasz Majewski wrote: > > Signed-off-by: Lukasz Majewski >=20 > please add a commit message with a short description of the change. >=20 > Also change subject line to "ARM: dts: imx6q: Add mccmon6 board > support". >=20 > > --- > > MCCMON6 board support depends on following patches: > >=20 > > 1. "video: backlight: pwm_bl: Initialize fb_bl_on[x] and use_count > > during pwm_backlight_probe()" > > http://patchwork.ozlabs.org/patch/708844/ > >=20 > > 2. "pwm: imx: Provide atomic operation for IMX PWM driver" > > http://patchwork.ozlabs.org/patch/708847/ - > > http://patchwork.ozlabs.org/patch/708843/ > >=20 > >=20 > > --- > > arch/arm/boot/dts/Makefile | 1 + > > arch/arm/boot/dts/imx6q-mccmon6.dts | 469 > > ++++++++++++++++++++++++++++++++++++ 2 files changed, 470 > > insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-mccmon6.dts > >=20 > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > > index c558ba7..7ce1080 100644 > > --- a/arch/arm/boot/dts/Makefile > > +++ b/arch/arm/boot/dts/Makefile > > @@ -382,6 +382,7 @@ dtb-$(CONFIG_SOC_IMX6Q) +=3D \ > > imx6q-h100.dtb \ > > imx6q-hummingboard.dtb \ > > imx6q-icore-rqs.dtb \ > > + imx6q-mccmon6.dtb \ > > imx6q-marsboard.dtb \ >=20 > Please add a new line preserving alphabetical order. >=20 > > imx6q-nitrogen6x.dtb \ > > imx6q-nitrogen6_max.dtb \ > > diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts > > b/arch/arm/boot/dts/imx6q-mccmon6.dts new file mode 100644 > > index 0000000..7445d01 > > --- /dev/null > > +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts > > @@ -0,0 +1,469 @@ > > +/* > > + * Copyright 2016 >=20 > Copyright holder is missing. >=20 > > + * > > + * Author: Lukasz Majewski > > + * > > + * This program is free software; you can redistribute it and/or > > modify > > + * it under the terms of the GNU General Public License version 2 > > as > > + * published by the Free Software Foundation. > > + * > > + */ >=20 > Please add an empty line here to improve readability. >=20 > > +/dts-v1/; >=20 > Please add an empty line here to improve readability. >=20 > > +#include "imx6q.dtsi" > > + > > +#include > > +#include > > + > > +/ { > > + model =3D "Monitor6 i.MX6 Quad Board"; >=20 > Missing hardware vendor name. >=20 > > + compatible =3D "mccmon6", "fsl,imx6q"; >=20 > Missing hardware vendor prefix before "mccmon6". "lwn,mccmon6" ? >=20 > > + > > + memory { > > + reg =3D <0x10000000 0x80000000>; > > + }; > > + > > + ethernet0 { > > + status =3D "okay"; > > + }; >=20 > It looks like a useless device node, you have a description of &fec > already. >=20 > > + > > + backlight_lvds: backlight { > > + compatible =3D "pwm-backlight"; > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_display>; >=20 > I would recommend to rename "pinctrl_display" to "pinctrl_backlight". >=20 > > + pwms =3D <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; >=20 > This should work when extension to the i.MX PWM driver is merged. Yes. The PWM -> apply is an ongoing work. But without the PMW patch the board is also fully operational (with reversed PWM :-) ) >=20 > > + brightness-levels =3D < 0 1 2 3 4 5 6 > > 7 8 9 > > + 10 11 12 13 14 15 16 > > 17 18 19 > > + 20 21 22 23 24 25 26 > > 27 28 29 > > + 30 31 32 33 34 35 36 > > 37 38 39 > > + 40 41 42 43 44 45 46 > > 47 48 49 > > + 50 51 52 53 54 55 56 > > 57 58 59 > > + 60 61 62 63 64 65 66 > > 67 68 69 > > + 70 71 72 73 74 75 76 > > 77 78 79 > > + 80 81 82 83 84 85 86 > > 87 88 89 > > + 90 91 92 93 94 95 96 > > 97 98 99 > > + 100 101 102 103 104 105 106 > > 107 108 109 > > + 110 111 112 113 114 115 116 > > 117 118 119 > > + 120 121 122 123 124 125 126 > > 127 128 129 > > + 130 131 132 133 134 135 136 > > 137 138 139 > > + 140 141 142 143 144 145 146 > > 147 148 149 > > + 150 151 152 153 154 155 156 > > 157 158 159 > > + 160 161 162 163 164 165 166 > > 167 168 169 > > + 170 171 172 173 174 175 176 > > 177 178 179 > > + 180 181 182 183 184 185 186 > > 187 188 189 > > + 190 191 192 193 194 195 196 > > 197 198 199 > > + 200 201 202 203 204 205 206 > > 207 208 209 > > + 210 211 212 213 214 215 216 > > 217 218 219 > > + 220 221 222 223 224 225 226 > > 227 228 229 > > + 230 231 232 233 234 235 236 > > 237 238 239 > > + 240 241 242 243 244 245 246 > > 247 248 249 > > + 250 251 252 253 254 255>; >=20 > I'm not sure that actually need such a long list of brightness levels. Such brightness-level property is so verbose on purpose - in this board we need fine brightness adjustment (harsh environment operation). >=20 > > + default-brightness-level =3D <50>; > > + enable-gpios =3D <&gpio1 2 GPIO_ACTIVE_LOW>; > > + }; > > + > > + reg_lvds: regulator-lvds { > > + compatible =3D "regulator-fixed"; > > + regulator-name =3D "lvds_ppen"; > > + regulator-min-microvolt =3D <3300000>; > > + regulator-max-microvolt =3D <3300000>; > > + regulator-boot-on; > > + gpio =3D <&gpio1 19 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + }; > > + > > + panel-lvds0 { > > + compatible =3D "innolux,g121x1-l03"; > > + backlight =3D <&backlight_lvds>; > > + power-supply =3D <®_lvds>; > > + > > + port { > > + panel_in_lvds0: endpoint { > > + remote-endpoint =3D <&lvds0_out>; > > + }; > > + }; > > + }; > > +}; > > + > > +&i2c1 { > > + clock-frequency =3D <100000>; > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_i2c1>; > > + status =3D "okay"; > > +}; > > + > > +&i2c2 { > > + clock-frequency =3D <100000>; > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_i2c2>; > > + status =3D "okay"; > > + > > + pmic: pfuze100@08 { > > + compatible =3D "fsl,pfuze100"; > > + reg =3D <0x08>; > > + > > + regulators { > > + sw1a_reg: sw1ab { > > + regulator-min-microvolt =3D <300000>; > > + regulator-max-microvolt =3D > > <1875000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay =3D <6250>; > > + }; > > + > > + sw1c_reg: sw1c { > > + regulator-min-microvolt =3D <300000>; > > + regulator-max-microvolt =3D > > <1875000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay =3D <6250>; > > + }; > > + > > + sw2_reg: sw2 { > > + regulator-min-microvolt =3D <800000>; > > + regulator-max-microvolt =3D > > <3950000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + sw3a_reg: sw3a { > > + regulator-min-microvolt =3D <400000>; > > + regulator-max-microvolt =3D > > <1975000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + sw3b_reg: sw3b { > > + regulator-min-microvolt =3D <400000>; > > + regulator-max-microvolt =3D > > <1975000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + sw4_reg: sw4 { > > + regulator-min-microvolt =3D <800000>; > > + regulator-max-microvolt =3D > > <3300000>; > > + }; > > + > > + swbst_reg: swbst { > > + regulator-min-microvolt =3D > > <5000000>; > > + regulator-max-microvolt =3D > > <5150000>; > > + }; > > + > > + snvs_reg: vsnvs { > > + regulator-min-microvolt =3D > > <1000000>; > > + regulator-max-microvolt =3D > > <3000000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vref_reg: vrefddr { > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen1_reg: vgen1 { > > + regulator-min-microvolt =3D <800000>; > > + regulator-max-microvolt =3D > > <1550000>; > > + }; > > + > > + vgen2_reg: vgen2 { > > + regulator-min-microvolt =3D <800000>; > > + regulator-max-microvolt =3D > > <1550000>; > > + }; > > + > > + vgen3_reg: vgen3 { > > + regulator-min-microvolt =3D > > <1800000>; > > + regulator-max-microvolt =3D > > <3300000>; > > + }; > > + > > + vgen4_reg: vgen4 { > > + regulator-min-microvolt =3D > > <1800000>; > > + regulator-max-microvolt =3D > > <3300000>; > > + regulator-always-on; > > + }; > > + > > + vgen5_reg: vgen5 { > > + regulator-min-microvolt =3D > > <1800000>; > > + regulator-max-microvolt =3D > > <3300000>; > > + regulator-always-on; > > + }; > > + > > + vgen6_reg: vgen6 { > > + regulator-min-microvolt =3D > > <1800000>; > > + regulator-max-microvolt =3D > > <3300000>; > > + regulator-always-on; > > + }; > > + }; > > + }; > > +}; > > + > > +&iomuxc { > > + pinctrl-names =3D "default"; > > + > > + imx6q-mccmon6 { > > + >=20 > Please drop the empty line above. >=20 > > + pinctrl_enet: enetgrp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 > > + > > MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 > > + > > MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 > > + > > MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 > > + MX6QDL_PAD_GPIO_16__ENET_REF_CLK > > 0x4001b0a8 > > + > > MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 > > + >; > > + }; > > + > > + pinctrl_i2c1: i2c1grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 > > + > > MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 > > + >; > > + }; > > + > > + pinctrl_i2c2: i2c2grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 > > + > > MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 > > + >; > > + }; > > + > > + pinctrl_uart1: uart1grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 > > + > > MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 > > + >; > > + }; > > + > > + pinctrl_usdhc2: usdhc2grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 > > + > > MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 > > + > > MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 > > + > > MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 > > + > > MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 > > + > > MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 > > + >; > > + }; > > + > > + pinctrl_usdhc3: usdhc3grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 > > + > > MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 > > + > > MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 > > + > > MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 > > + > > MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 > > + > > MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 > > + > > MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 > > + > > MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 > > + > > MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 > > + > > MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 > > + > > MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 > > + >; > > + }; > > + > > + pinctrl_weim_cs0: weimcs0grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 > > + >; > > + }; > > + > > + pinctrl_weim_nor: weimnorgrp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 > > + > > MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 > > + > > MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 > > + > > MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 > > + > > MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 > > + > > MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 > > + > > MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 > > + > > MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 > > +v4.9-release-devel-fast > > MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 > > + > > MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 > > + > > MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 > > + > > MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 > > + > > MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 > > + > > MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 > > + >; > > + }; > > + > > + pinctrl_ecspi3: ecspi3grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 > > + > > MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 > > + > > MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 > > + >; > > + }; > > + > > + pinctrl_ecspi3_cs: ecspi3cs { > > + fsl,pins =3D < > > + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 > > 0x80000000 > > + >; > > + }; > > + pinctrl_ecspi3_flwp: ecspi3flwp { > > + fsl,pins =3D < > > + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 > > 0x80000000 > > + >; > > + }; > > + > > + pinctrl_uart4: uart4grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 > > + > > MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 > > + > > MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 > > + > > MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 > > + >; > > + }; > > + > > + pinctrl_display: dispgrp { > > + fsl,pins =3D < > > + /* BLEN_OUT */ > > + MX6QDL_PAD_GPIO_2__GPIO1_IO02 > > 0x1b0b0 > > + /* LVDS_PPEN_OUT */ > > + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 > > 0x1b0b0 >=20 > This GPIO should be moved to a pinctrl group of regulator-lvds device > node. You mean to provide separate: pinctrl_reg_lvds: req_lvds_grp { fsl,pins =3D < /* LVDS_PPEN_OUT */ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 >; and then reg_lvds: regulator-lvds { compatible =3D "regulator-fixed"; regulator-name =3D "lvds_ppen"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-boot-on; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_reg_lvds>; gpio =3D <&gpio1 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; >=20 > > + >; > > + }; > > + > > + pinctrl_pwm2: pwm2grp { > > + fsl,pins =3D < > > + > > MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 > > + >; > > + }; >=20 > Please sort out all pinctrl_* nodes alphabetically. >=20 > > + }; > > +}; > > + > > +&fec { > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_enet>; > > + phy-mode =3D "rgmii"; > > + phy-reset-gpios =3D <&gpio1 27 0>; >=20 > GPIO1_27 has no pad configuration in pinctrl_enet. >=20 > > + interrupts-extended =3D <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; > > + status =3D "okay"; > > +}; > > + > > +&uart1 { > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_uart1>; >=20 > Should you add "uart-has-rtscts" property? This is a simple "console" uart without rts/cts, so this property is not needed. >=20 > > + status =3D "okay"; > > +}; > > + > > +&usdhc2 { > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_usdhc2>; > > + cd-gpios =3D <&gpio1 4 GPIO_ACTIVE_LOW>; >=20 > bus-width =3D <4>; >=20 > You should consider to add the GPIO1_4 into pinctrl_usdhc2 group. Added. >=20 > > + status =3D "okay"; > > +}; > > + > > +&usdhc3 { > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_usdhc3>; > > + bus-width =3D <8>; > > + status =3D "okay"; >=20 > No "cd-gpios" property, should you add "non-removable" property then? Yes, this is the eMMC memory. >=20 > > +}; > > + > > +&weim { > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_weim_nor &pinctrl_weim_cs0>; > > + #address-cells =3D <2>; > > + #size-cells =3D <1>; > > + ranges =3D <0 0 0x08000000 0x08000000>; > > + status =3D "okay"; > > + > > + nor@0,0 { > > + compatible =3D "cfi-flash"; > > + reg =3D <0 0 0x02000000>; > > + #address-cells =3D <1>; > > + #size-cells =3D <1>; > > + bank-width =3D <2>; > > + use-advanced-sector-protection; > > + fsl,weim-cs-timing =3D <0x00620081 0x00000001 > > 0x1c022000 > > + 0x0000c000 0x1404a38e 0x00000000>; > > + }; > > +}; > > + > > +&ecspi3 { > > + fsl,spi-num-chipselects =3D <1>; >=20 > This property is obsoleted, please remove it. >=20 > > + cs-gpios =3D <&gpio4 24 0>; > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_ecspi3 &pinctrl_ecspi3_cs > > &pinctrl_ecspi3_flwp>; > > + status =3D "okay"; > > + > > + flash: s25sl032p@0 { > > + #address-cells =3D <1>; > > + #size-cells =3D <1>; > > + compatible =3D "spansion,s25sl032p", "jedec,spi-nor"; > > + spi-max-frequency =3D <40000000>; > > + reg =3D <0>; > > + }; > > +}; > > + > > +&uart4 { > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_uart4>; > > + status =3D "okay"; >=20 > Should you add "uart-has-rtscts" property? Yes, this uart supports rts/cts flow controll >=20 > > +}; > > + > > +&ldb { > > + status =3D "okay"; > > + > > + lvds0: lvds-channel@0 { > > + fsl,data-mapping =3D "spwg"; > > + fsl,data-width =3D <24>; > > + status =3D "okay"; > > + > > + port@4 { > > + reg =3D <4>; > > + > > + lvds0_out: endpoint { > > + remote-endpoint =3D > > <&panel_in_lvds0>; > > + }; > > + }; > > + }; > > +}; > > + > > +&pwm2 { > > + #pwm-cells =3D <3>; > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pinctrl_pwm2>; > > + status =3D "okay"; > > +}; > >=20 >=20 > Please sort out all device nodes but &iomuxc alphabetically: >=20 > * iomuxc > * ecspi3 > * fec > * i2c1 > * i2c2 > * ldb > * pwm2 > * uart1 > * uart4 > * usdhc2 > * usdhc3 > * weim Ok. >=20 > -- > With best wishes, > Vladimir Best regards, =C5=81ukasz Majewski --Sig_/.0NNA_UA99nYKxyeYOjmUKR Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlhqZ1sACgkQf9/hG2YwgjEgOQCgtPFmQms+px8Q9Cfh2VwJFEXW pg8AoMtwRU04dIF14md5RCGIQI35Mriz =Vyv5 -----END PGP SIGNATURE----- --Sig_/.0NNA_UA99nYKxyeYOjmUKR--