From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758364AbdADLA7 (ORCPT ); Wed, 4 Jan 2017 06:00:59 -0500 Received: from foss.arm.com ([217.140.101.70]:48312 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752933AbdADLA7 (ORCPT ); Wed, 4 Jan 2017 06:00:59 -0500 Date: Wed, 4 Jan 2017 10:53:49 +0000 From: Mark Rutland To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, kim.phillips@arm.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, tglx@linutronix.de, peterz@infradead.org, alexander.shishkin@linux.intel.com, robh@kernel.org, suzuki.poulose@arm.com, pawel.moll@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 02/10] arm64: cpufeature: Don't enforce system-wide SPE capability Message-ID: <20170104105349.GC8329@leverpostej> References: <1483467027-14547-1-git-send-email-will.deacon@arm.com> <1483467027-14547-3-git-send-email-will.deacon@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1483467027-14547-3-git-send-email-will.deacon@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 03, 2017 at 06:10:19PM +0000, Will Deacon wrote: > The statistical profiling extension (SPE) is an optional feature of > ARMv8.1 and is unlikely to be supported by all of the CPUs in a > heterogeneous system. > > This patch updates the cpufeature checks so that such systems are not > tainted as unsupported. > > Reviewed-by: Suzuki Poulose > Signed-off-by: Will Deacon I couldn't find this in the ARMV8.1 supplement, but it is in the SPE spec. FWIW: Acked-by: Mark Rutland > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kernel/cpufeature.c | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 98ae03f8eedd..e156e7793a65 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -190,6 +190,7 @@ > #define ID_AA64MMFR2_CNP_SHIFT 0 > > /* id_aa64dfr0 */ > +#define ID_AA64DFR0_PMSVER_SHIFT 32 > #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 > #define ID_AA64DFR0_WRPS_SHIFT 20 > #define ID_AA64DFR0_BRPS_SHIFT 12 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 47d0226620e8..c18eb78d3a00 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -180,7 +180,8 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { > - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), > + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 36, 28, 0), As a heads-up, this line will disappear with Suzuki's cpufeature updates series, so you may spot a clash later on. Thanks, Mark. > + ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), > -- > 2.1.4 >