From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935958AbdAERsK (ORCPT ); Thu, 5 Jan 2017 12:48:10 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:36322 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753846AbdAERrj (ORCPT ); Thu, 5 Jan 2017 12:47:39 -0500 Date: Thu, 5 Jan 2017 18:47:25 +0100 From: Maxime Ripard To: Andre Przywara Cc: Ulf Hansson , Chen-Yu Tsai , Hans De Goede , Icenowy Zheng , Mark Rutland , Rob Herring , devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/5] drivers: mmc: sunxi: fix A64 calibration routine Message-ID: <20170105174725.kmr25iodjnjozqjm@lukather> References: <1483398226-29321-1-git-send-email-andre.przywara@arm.com> <1483398226-29321-2-git-send-email-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="enoc76q3xwcga7iz" Content-Disposition: inline In-Reply-To: <1483398226-29321-2-git-send-email-andre.przywara@arm.com> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --enoc76q3xwcga7iz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Mon, Jan 02, 2017 at 11:03:42PM +0000, Andre Przywara wrote: > The calibration facility in the A64 MMC block seems to have been > misunderstood: the result value is not the value to program into the > delay bits, but is the number of delay cells that result in a full clock > cycle delay. So this value has to be scaled by the desired phase, which > we still have to know and program. > Change the calibration routine to take a phase parameter and scale the > calibration value accordingly. > Also introduce sun50i-a64 delay parameters to store the required phase. > Looking at the BSP kernel the sample delay for anything below HS200 is > 0, so we go with that value. > Once the driver supports HS200 and faster modes, we can enter confirmed > working values in there. >=20 > Signed-off-by: Andre Przywara Exactly how that works hasn't been confirmed, and the only thing that this patch actually do is... nothing, since the delay is always 0. If and when we get HS400 to work and we know for a fact how the calibration works, then we'll be able to use it. Until then, we can just clear those bits. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --enoc76q3xwcga7iz Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJYboaoAAoJEBx+YmzsjxAgTxQQAL91c7Q3WnLms7gk0GRrXI6Y yzSYcRZLRV5kzVPGauEpATw+St4umjrNe1qQUU+NrPWlfUngu6H3YVMqgUOMj/T4 VdfXl9Xf/ECkKYLk+6n06zRGBmeqss2D3b472TAuwGzokqTtR6oorgd+6lfTu/Z0 yK6k8MEYpkP3R1/KsAp1lCvrYrg/reKeTXYiQGj05TGa+q2Huqu4C1nEgZkWPpoq 8ekUXa71y8p+ox+bDh9FklskiJBX7q6iu+ejb0fMg1eHohakaTeOrHH42RPwx0Cb rsvd21KUDCJF31mScK+OLxRSmyWBgtBTStZyUsL71Gr1vDtJ5ZgMQUaCxaohrmSf ovgqfHEMbA/NTDbYIuVC/fD37Z1D/7PdOkiOK/bH0FBf8vZvYeEpYJOw6ql5NNvc ZymnGmOoODFBfen40tLt1Fk+gWcrGu0uYsOCGjLKuKOu75CI74HLmqxAuA7HM0B0 gDURBa1VWkgliQGhZYAJD7LFNiD3inHExMr55DQFcvctd+BcXPFW42dYPk/Z8y4S KqBJo919lpnrVUxuN87edwsljiP91pSPdp3llXit1KlqIY1gFkMNcczrH13kmHj/ GpDqjCJzud76eDw7+p/8pQ7as+xckLVFzLKFb74XHOt/9+zwxbiay2B/t6MfaU1H 3DaO9Qxn0docCsWEY4BY =RP2u -----END PGP SIGNATURE----- --enoc76q3xwcga7iz--