From: Peter Zijlstra <peterz@infradead.org>
To: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
joro@8bytes.org, bp@alien8.de, mingo@redhat.com
Subject: Re: [PATCH v7 1/7] perf/amd/iommu: Misc fix up perf_iommu_read
Date: Wed, 11 Jan 2017 12:57:35 +0100 [thread overview]
Message-ID: <20170111115735.GI3107@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1484019227-11473-2-git-send-email-Suravee.Suthikulpanit@amd.com>
On Mon, Jan 09, 2017 at 09:33:41PM -0600, Suravee Suthikulpanit wrote:
> This patch contains the following minor fixup:
> * Fixed overflow handling since u64 delta would lose the MSB sign bit.
Please explain.. afaict this actually introduces a bug.
> diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
> index b28200d..f387baf 100644
> --- a/arch/x86/events/amd/iommu.c
> +++ b/arch/x86/events/amd/iommu.c
> @@ -319,29 +319,30 @@ static void perf_iommu_start(struct perf_event *event, int flags)
>
> static void perf_iommu_read(struct perf_event *event)
> {
> - u64 count = 0ULL;
> - u64 prev_raw_count = 0ULL;
> - u64 delta = 0ULL;
> + u64 cnt, prev;
> + s64 delta;
> struct hw_perf_event *hwc = &event->hw;
> pr_debug("perf: amd_iommu:perf_iommu_read\n");
>
> amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
> _GET_BANK(event), _GET_CNTR(event),
> - IOMMU_PC_COUNTER_REG, &count, false);
> + IOMMU_PC_COUNTER_REG, &cnt, false);
>
> /* IOMMU pc counter register is only 48 bits */
> - count &= 0xFFFFFFFFFFFFULL;
> + cnt &= GENMASK_ULL(48, 0);
>
> - prev_raw_count = local64_read(&hwc->prev_count);
> - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
> - count) != prev_raw_count)
> - return;
> + prev = local64_read(&hwc->prev_count);
>
> - /* Handling 48-bit counter overflowing */
> - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT);
> + /*
> + * Since we do not enable counter overflow interrupts,
> + * we do not have to worry about prev_count changing on us.
> + */
So you cannot group this event with a software event that reads this
from their sample?
> + local64_set(&hwc->prev_count, cnt);
> +
> + /* Handle 48-bit counter overflow */
> + delta = (cnt << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
> delta >>= COUNTER_SHIFT;
> local64_add(delta, &event->count);
> -
> }
>
> static void perf_iommu_stop(struct perf_event *event, int flags)
> --
> 1.8.3.1
>
next prev parent reply other threads:[~2017-01-11 11:57 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-10 3:33 [PATCH v7 0/7] perf/amd/iommu: Enable multi-IOMMU support Suravee Suthikulpanit
2017-01-10 3:33 ` [PATCH v7 1/7] perf/amd/iommu: Misc fix up perf_iommu_read Suravee Suthikulpanit
2017-01-11 10:32 ` Borislav Petkov
2017-01-11 11:57 ` Peter Zijlstra [this message]
2017-01-15 2:36 ` Suravee Suthikulpanit
2017-01-19 10:14 ` Peter Zijlstra
2017-01-10 3:33 ` [PATCH v7 2/7] perf/amd/iommu: Modify functions to query max banks and counters Suravee Suthikulpanit
2017-01-10 14:43 ` Joerg Roedel
2017-01-11 3:03 ` Suravee Suthikulpanit
2017-01-11 8:13 ` Boris Petkov
2017-01-11 9:14 ` Suravee Suthikulpanit
2017-01-10 3:33 ` [PATCH v7 3/7] perf/amd/iommu: Modify IOMMU API to allow specifying IOMMU index Suravee Suthikulpanit
2017-01-11 17:23 ` Borislav Petkov
2017-01-10 3:33 ` [PATCH v7 4/7] perf/amd/iommu: Declare pr_fmt and remove unnecessary pr_debug Suravee Suthikulpanit
2017-01-12 10:19 ` Borislav Petkov
2017-01-14 10:13 ` Suravee Suthikulpanit
2017-01-10 3:33 ` [PATCH v7 5/7] perf/amd/iommu: Clean up perf_iommu_enable_event Suravee Suthikulpanit
2017-01-12 14:14 ` Borislav Petkov
2017-01-10 3:33 ` [PATCH v7 6/7] iommu/amd: Introduce amd_iommu_get_num_iommus() Suravee Suthikulpanit
2017-01-12 14:21 ` Borislav Petkov
2017-01-10 3:33 ` [PATCH v7 7/7] perf/amd/iommu: Enable support for multiple IOMMUs Suravee Suthikulpanit
2017-01-12 17:52 ` Borislav Petkov
2017-01-13 10:24 ` Suravee Suthikulpanit
2017-01-13 11:49 ` Borislav Petkov
2017-01-14 2:58 ` Suravee Suthikulpanit
2017-01-14 10:29 ` Borislav Petkov
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