From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751382AbdAPNHy (ORCPT ); Mon, 16 Jan 2017 08:07:54 -0500 Received: from dougal.metanate.com ([90.155.101.14]:5449 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751075AbdAPNHw (ORCPT ); Mon, 16 Jan 2017 08:07:52 -0500 X-Greylist: delayed 1331 seconds by postgrey-1.27 at vger.kernel.org; Mon, 16 Jan 2017 08:07:51 EST Date: Mon, 16 Jan 2017 12:44:53 +0000 From: John Keeping To: Chris Zhong Cc: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de, yzq@rock-chips.com, mark.rutland@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, pawel.moll@arm.com, seanpaul@chromium.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Mark Yao Subject: Re: [PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel Message-ID: <20170116124453.2154def9.john@metanate.com> In-Reply-To: <1484561311-494-12-git-send-email-zyw@rock-chips.com> References: <1484561311-494-1-git-send-email-zyw@rock-chips.com> <1484561311-494-12-git-send-email-zyw@rock-chips.com> Organization: Metanate Ltd X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote: > Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough > for some panel, it will cause the screen display is not normal, so > increases the badnwidth to 1 / 0.8. > > Signed-off-by: Chris Zhong > > --- > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 9dfa73d..5a973fe 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -501,8 +501,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi) > > mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC); > if (mpclk) { > - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ > - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9; > + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ > + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8; This and patch 9 are just hacking around the underlying problem in order to make particular panels work. I'm pretty sure the actual issue is the use of hardcoded values when configuring the PHY, since the PHY parameters are specified in clock cycles but the MIPI spec requires absolute time durations. I posted a series addressing this a while ago, although I screwed up sending it so some patches were included twice and since no one expressed any interest I didn't post a cleaned up version. The relevant patch is here: https://patchwork.kernel.org/patch/9340193/ > if (tmp < max_mbps) > target_mbps = tmp; > else