From: Will Deacon <will.deacon@arm.com>
To: Tomasz Nowicki <tn@semihalf.com>
Cc: robin.murphy@arm.com, mark.rutland@arm.com, joro@8bytes.org,
Linu.Cherian@cavium.com, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
Sunil.Goutham@cavium.com, Geethasowjanya.Akula@cavium.com,
Tirumalesh.Chalamarla@cavium.com, Prasun.Kapoor@cavium.com
Subject: Re: [PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704
Date: Thu, 19 Jan 2017 16:16:16 +0000 [thread overview]
Message-ID: <20170119161615.GH31594@arm.com> (raw)
In-Reply-To: <1484550967-6328-1-git-send-email-tn@semihalf.com>
On Mon, Jan 16, 2017 at 08:16:07AM +0100, Tomasz Nowicki wrote:
> The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs
> are unique across all SMMU instances on affected Cavium systems.
>
> Currently, the workaround code partitions ASIDs and VMIDs by increasing
> global cavium_smmu_context_count which in turn becomes the base ASID and VMID
> value for the given SMMU instance upon the context bank initialization.
>
> For systems with multiple SMMU instances this approach implies the risk
> of crossing 8-bit ASID, like for 1-socket CN88xx capable of 4 SMMUv2,
> 128 context banks each:
> SMMU_0 (0-127 ASID RANGE)
> SMMU_1 (127-255 ASID RANGE)
> SMMU_2 (256-383 ASID RANGE) <--- crossing 8-bit ASID
> SMMU_3 (384-511 ASID RANGE) <--- crossing 8-bit ASID
>
> Since now we use 8-bit ASID (SMMU_CBn_TCR2.AS = 0) we effectively misconfigure
> ASID[15:8] bits of SMMU_CBn_TTBRm register for SMMU_2/3. Moreover, we still
> assume non-zero ASID[15:8] bits upon context invalidation. In the end,
> except SMMU_0/1 devices all other devices under other SMMUs will fail on guest
> power off/on. Since we try to invalidate TLB with 16-bit ASID but we actually
> have 8-bit zero padded 16-bit entry.
>
> This patch adds 16-bit ASID support for stage-1 AArch64 contexts so that
> we use ASIDs consistently for all SMMU instances.
>
> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Reviewed-by: Tirumalesh Chalamarla <Tirumalesh.Chalamarla@cavium.com>
> ---
> drivers/iommu/arm-smmu.c | 3 +++
> 1 file changed, 3 insertions(+)
Thanks, queued for 4.11.
Will
next prev parent reply other threads:[~2017-01-19 16:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-16 7:16 [PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704 Tomasz Nowicki
2017-01-16 7:25 ` Tomasz Nowicki
2017-01-19 16:16 ` Will Deacon [this message]
-- strict thread matches above, loose matches on Subject: below --
2017-01-11 11:51 Tomasz Nowicki
2017-01-11 12:19 ` Robin Murphy
2017-01-12 6:41 ` Tomasz Nowicki
2017-01-13 10:43 ` Tomasz Nowicki
2017-01-13 10:54 ` Robin Murphy
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